Publications

Books

  1. R. Gao, F. Ye, G. Luo, J. Cong, . Smartphone-Based Indoor Map Construction: Principles and Applications. Springer Singapore, 2018.
  2. Y-T. Chen, J. Cong, M. Gill, G. Reinman, and B. Xiao. Customizable Computing - Synthesis Lectures on Computer Architecture. Morgan and Claypool Publishers, July 2015.
  3. Y. Xie, J. Cong and S. Sapatnekar, editors. Three-Dimensional Integrated Circuit Design: EDA, Design and Microarchitectures. Springer Publishers, 2009.
  4. G.-J. Nam and J. Cong, editors. Modern Circuit Placement. Springer Publishers, 2007.
  5. J. Cong and J. Shinnerl, editors. Multilevel Optimization in VLSICAD. Kluwer Academic Publishers, 2003.
  6. R. Liberskind-Hadas, N. Hasan, J. Cong, P. Mckinley and C. L. Liu. Fault Covering Problems in Reconfigurable VLSI Systems. Kluwer Academic Publishers, 1992.

Book chapters

  1. Bochen Tan and Jason Cong. Layout Synthesis for Near-Term Quantum Computing: Gap Analysis and Optimal Solution. In Design Automation of Quantum Computers, R. O. Topaloglu, Ed. Cham: Springer International Publishing, 2023, pp. 25–40.
  2. J. Cong, M. Huang, P. Pan, Y. Wang, P. Zhang. Source-to-Source Optimization for HLS. ed. Dirk Koch, Frank Hannig, Daniel Ziener, Springer Publishers. 2016.
  3. J. Cong and G. Luo, "Thermal-Aware 3D Placement,". Three-Dimensional Integrated Circuit Design: EDA, Design and Microarchitectures. ed. Y. Xie, J. Cong and S. Sapatnekar, Springer Publishers, 2009.
  4. J. Cong and Y. Ma, "Thermal-Aware 3D Floorplan,". Three-Dimensional Integrated Circuit Design: EDA, Design and Microarchitectures. ed. Y. Xie, J. Cong and S. Sapatnekar, Springer Publishers, 2009.
  5. Z. Zhang, Y. Fan, W. Jiang, G. Han, C. Yang, and J. Cong, "AutoPilot: A Platform-Based ESL Synthesis System,". High-Level Synthesis: From Algorithm to Digital Circuit. ed. P. Coussy and A. Morawiec, Springer Publishers, 2008.
  6. T. F. Chan, J. Cong, J. Shinnerl, K. Sze, and M. Xie, "mPL6: Enhancement Multilevel Mixed-Size Placement with Congestion Control,". Modern Circuit Placement. ed. G.-J. Nam and J. Cong, Springer Publishers, 2007, pp. 247-288.
  7. J. Cong, M. Romesis, J. Shinnerl, K. Sze, and M. Xie, "Locality and Utilization in Placement Suboptimality ,". Modern Circuit Placement. ed. G.-J. Nam and J. Cong, Springer Publishers, 2007, pp.13-36.
  8. J. Cong and P. Pan, "Technology Mapping,". Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation (Systems on Silicon). ed. S. Hauck and A. DeHon, Morgan Kaufmann, 2007, pp. 277-296.
  9. J. Cong and J.R. Shinnerl, "Large-Scale Global Placement,". Approximation Algorithms and Metaheuristics. CRC Press, 2006, pp. 79-1--79-19.
  10. T. F. Chan, J. Cong, J. Shinnerl, K. Sze, M. Xie and Y. Zhang. Multiscale Optimization in VLSI Physical Design Automation. Springer Publishers, 2005, pp. 1-68.
  11. J. Cong, M. Xie, and Y. Zhang, "Multilevel VLSI Routing,". Multilevel Optimization in VLSICAD. ed. J. Cong and J. Shinnerl, Kluwer Academic Publishers, 2003, pp. 195-217.
  12. T. F. Chan, J. Cong, T. Kong, and J. Shinnerl, "Multilevel Circuit Planning,". Multilevel Optimization in VLSICAD. ed. J. Cong and J. Shinnerl, Kluwer Academic Publishers, 2003, pp. 155-193.
  13. J. Cong, "Interconnect Planning". Layout Optimization in VLSI Design. ed. B. Lu, D.-Z. Du and S. S. Sapatnekar, Network Theory and Applications Series, Kluwer Academic Publishers, 2001, pp. 19-44.
  14. J. Cong, L. He and C. K. Koh,"Layout Optimization,". Low Power Design in Deep Submicron Electronics. ed. W. Nebel and J. Mermet, NATO ASI Series, Kluwer Academic Publishers, 1997, pp. 205-266.

Journal publications

  1. Atefeh Sohrabizadeh, Yunsheng Bai, Yizhou Sun, Jason Cong. Harnessing GNNs for Robust Representation Learning in High-Level Synthesis. IEEE Transactions on Circuits and Systems for Artificial Intelligence (Early Access), pp 1-11, October 24, 2024. DOI: 10.1109/TCASAI.2024.3485522.
  2. Moazin Khatti, Xingyu Tian, Ahmad Sedigh Baroughi, Akhil Raj Baranwal, Yuze Chi, Licheng Guo, Jason Cong, Zhenman Fang. PASTA: Programming and Automation Support for Scalable Task-Parallel HLS Programs on Modern Multi-Die FPGAs. ACM Transactions on Reconfigurable Technology and Systems, Vol. 17, No. 3, September 30, 2024.
  3. Liqiang Lu, Zizhang Luo, Size Zheng, Jieming Yin, Jason Cong, Yun Liang, Jianwei Yin. Rubick: A Unified Infrastructure for Analyzing, Exploring, and Implementing Spatial Architectures via Dataflow Decomposition. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 43, Issue 4, pp. 1177-1190, April 2024, DOI: 10.1109/TCAD.2023.3337208.
  4. Daniel Bochen Tan, Dolev Bluvstein, Mikhail D. Lukin, and Jason Cong. Compiling Quantum Circuits for Dynamically Field-Programmable Neutral Atoms Array Processors. Quantum, Vol. 8, pp.1281, March 14, 2024.
  5. Licheng Guo, Yuze Chi, Jason Lau, Linghao Song, Xingyu Tian, Moazin Khatti, Weikang Qiao, Jie Wang, Ecenur Ustun, Zhenman Fang, Zhiru Zhang and Jason Cong. TAPA: A Scalable Task-Parallel Dataflow Programming Framework for Modern FPGAs with Co-Optimization of HLS and Physical Design. ACM Transactions on Reconfigurable Technology and Systems, Volume 16, Issue 4, Article No.: 63, pp 1–31, December 5, 2023.
  6. Gert Cauwenberghs, Jason Cong, X. Sharon Hu, Subhasish Mitra, Wolfgang Porod, H.-S. Philip Wong. Point of View: Micro/Nano Circuits and Systems Design and Design Automation: Challenges and Opportunities. Proceedings of the IEEE, Vol 111, Issue 6, pp 561-574, June 2023.
  7. Licheng Guo, Pongstorn Maidee, Yun Zhou, Chris Lavin, Eddie Hung, Wuxi Li, Jason Lau, Weikang Qiao, Yuze Chi, Linghao Song, Yuanlong Xiao, Alireza Kaviani, Zhiru Zhang, Jason Cong. RapidStream 2.0: Automated Parallel Implementation of Latency Insensitive FPGA Designs Through Partial Reconfiguration. ACM Transactions on Reconfigurable Technology and Systems, April 26, 2023, https://doi.org/10.1145/3593025.
  8. Zhe Chen, Garrett J. Blair, Chengdi Cao, Jim Zhou, Daniel Aharoni, Peyman Golshani, Hugh T. Blair, and Jason Cong. FPGA-Based In-Vivo Calcium Image Decoding for Closed-Loop Feedback Applications. IEEE Transactions on Biomedical Circuits and Systems. Volume 17, Issue 2, pp. 169-179, April 2023. DOI: 10.1109/TBCAS.2023.3268130.
  9. Young-kyu Choi, Carlos Santillana, Yujia Shen, Adnan Darwiche, Jason Cong. FPGA Acceleration of Probabilistic Sentential Decision Diagrams with High-Level Synthesis. ACM Transactions on Reconfigurable Technology and Systems, Vol 16, Issue 2, Article 18, pp 1-22, March 11, 2023.
  10. Suhail Basalama, Atefeh Sohrabizadeh, Jie Wang, Licheng Guo, and Jason Cong. FlexCNN: An End-to-End Framework for Composing CNN Accelerators on FPGA. ACM Transactions on Reconfigurable Technology and Systems, Vol 16, Issue 2, Article 23, pp 1-32, March 11, 2023.
  11. Zhe Chen, Garrett J Blair, Changliang Guo, Jim Zhou, Juan-Luis Romero-Sosa, Alicia Izquierdo, Peyman Golshani, Jason Cong, Daniel Aharoni, and Hugh T Blair. A hardware system for real time decoding of in vivo calcium imaging data. eLife, 12:e78344, Jan 24, 2023. DOI: 10.7554/eLife.78344.
  12. Yuze Chi, Weikang Qiao, Atefeh Sohrabizadeh, Jie Wang, Jason Cong. Democratizing Domain-Specific Computing. Communications of the ACM, Volume 66, Issue 1, January 2023, pp 74–85, https://doi.org/10.1145/3524108.
  13. Weikang Qiao, Licheng Guo, Zhenman Fang, Mau-Chung Frank Chang, and Jason Cong. TopSort: A High-Performance Two-Phase Sorting Accelerator Optimized on HBM-based FPGAs. IEEE Transactions on Emerging Topics in Computing, pp. 1-15, December 19, 2022, DOI: 10.1109/TETC.2022.3228575.
  14. Young-kyu Choi, Yuze Chi, Jason Lau, and Jason Cong . TARO: Automatic Optimization for Free-Running Kernels in FPGA HLS. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 41, No. 12, December 2022, DOI: 10.1109/TCAD.2022.3216544.
  15. Jason Cong, Jason Lau, Gai Liu, Stephen Neuendorffer, Peichen Pan, Kees Vissers, Zhiru Zhang. FPGA HLS Today: Successes, Challenges, and Opportunities. ACM Transactions on Reconfigurable Technology and Systems, Volume 15, Issue 4, Article No. 5, pp 1–42, December 2022, https://doi.org/10.1145/3530775.
  16. Zhe Chen, Hugh T. Blair, Jason Cong. Energy Efficient LSTM Inference Accelerator for Real-Time Causal Prediction. ACM Transactions on Design Automation of Electronic Systems, Volume 27, Issue 5, Article 44, pp 1-19, September 2022, DOI 10.1145/3495006.
  17. Wan-Hsuan Lin, Bochen Tan, Murphy Yuezhen Niu, Jason Kimko, and Jason Cong. Domain-Specific Quantum Architecture Optimization. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, pp 624-637, Vol 12, Issue 3, September 2022, DOI: 10.1109/JETCAS.2022.3202870.
  18. Atefeh Sohrabizadeh, Cody Hao Yu, Min Gao, and Jason Cong. AutoDSE: Enabling Software Programmers to Design Efficient FPGA Accelerators. ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol 27, Issue 4, Article 32, pp 1-27, July 2022, DOI:10.1145/3494534 (Best Paper Award).
  19. Bochen Tan and Jason Cong. Optimality Study of Existing Quantum Computing Layout Synthesis Tools. IEEE Transactions on Computers, Vol 70, Issue 9, pp 1363 - 1373, September 1, 2021, DOI 10.1109/TC.2020.3009140.
  20. Meng Li, William Hsu, Xiaodong Xie, Jason Cong, and Wen Gao. SACNN: Self-Attention Convolutional Neural Network for Low-Dose CT Denoising with Self-supervised Perceptual Loss Network. IEEE Transactions on Medical Imaging, Vol 39, Issue 7, pp. 2289 – 2301, July 2020. DOI:10.1109/TMI.2020.2968472.
  21. Giovanni De Micheli, Antun Domic, Massimiliano Di Ventra, Martin Roettler, and Jason Cong. 2019 DAC Roundtable . IEEE Design & Test, Vol 37, Issue 3, pp. 100-114, June 2020. DOI: 10.1109/MDAT.2020.2968279.
  22. Yijin Guan, Guangyu Sun, Zhihang Yuan, Xingchen Li, Ningyi Xu, Shu Chen, Jason Cong, and Yuan Xie. Crane: Mitigating Accelerator Under-utilization Caused by Sparsity Irregularities in CNNs. IEEE Transactions on Computer, Vol: 69, Issue: 7, DOI: 10.1109/TC.2020.2981080, March 18, 2020.
  23. Young-kyu Choi, Yuze Chi, Jie Wang,and Jason Cong. FLASH: Fast, ParalleL, and Accurate Simulator for HLS. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 39, no. 12, pp. 4828 - 4841, Dec. 2020, DOI: 10.1109/TCAD.2020.2970597.
  24. Chen Zhang, Guangyu Sun, Zhenman Fang, Peipei Zhou, Peichen Pan, Jason Cong. Caffeine: Towards Uniformed Representation and Acceleration for Deep Convolutional Neural Networks. The IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 38, No. 11, pp. 2072-2085, November 2019, DOI: 10.1109/TCAD.2017.2785257 (2019 TCAD Donald O. Pederson Best Paper Award).
  25. Yanghyo Kim, Boyu Hu, Yuan Du, Wei-Han Cho, Rulin Huang, Adrian Tang, Huan-Neng Chen, Chewnpu Jou, Jason Cong, Tatsuo Itoh, and Mau-Chung Frank Chang. A Millimeter-Wave CMOS Transceiver With Digitally Pre-Distorted PAM-4 Modulation for Contactless Communications. IEEE Journal of Solid-State Circuits, Volume 54, Issue 6, pp. 1600-1612, June 2019. DOI: 10.1109/JSSC.2019.2896413.
  26. Yu-Heng Cheng, Yu-Chih Chen, Eric Lin, Riley Brien, Seungwon Jung, Yu-Ting Chen, Woncheol Lee, Zhijian Hao, Saswat Sahoo, Hyun Min Kang, Jason Cong, Monika Burness, Sunitha Nagrath, Max S. Wicha, and Euisik Yoon. Hydro-Seq enables contamination-free high-throughput single-cell RNA-sequencing for circulating tumor cells. Nature Communications, Vol 10, Article 2163, May 2019. DOI:10.1038/s41467-019-10122-2.
  27. Young-kyu Choi, Jason Cong, Zhenman Fang, Yuchen Hao, Glenn Reinman, and Peng Wei. In-Depth Analysis on Microarchitectures of Modern Heterogeneous CPU-FPGA Platforms. ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 12, no. 1, Feb. 2019. DOI:10.1145/3294054.
  28. Shuo Li, Nong Xiao, Peng Wang, Guangyu Sun, Xiaoyang Wang, Yiran Chen, Hai (Helen) Li, Jason Cong, Tao Zhang. RC-NVM: Dual-Addressing Non-Volatile Memory Architecture Supporting Both Row and Column Memory Accesses. IEEE Transactions on Computers, Volume 68, Issue 2, pp. 239-254, February 2019, DOI: 10.1109/TC.2018.2868368. (Paper of the Month).
  29. Jason Cong, Zhenman Fang, Muhuan Huang, Peng Wei, Di Wu, and Cody Hao Yu. Customizable Computing– From Single Chip to Datacenters. Proceedings of the IEEE, Volume 107, Issue 1, pp. 185-203, January 2019, DOI: 10.1109/JPROC.2018.2876372. (Invited paper).
  30. Xiaowei Xu , Yukun Ding, Sharon Xiaobo Hu, Michael Niemier, Jason Cong, Yu Hu, and Yiyu Shi. Scaling for edge inference of deep neural networks. Nature Electronics, Vol 1, pp. 216-222, April 2018.
  31. Jason Cong, Zhenman Fang, Muhuan Huang, Libo Wang, Di Wu. CPU-FPGA Co-Scheduling for Big Data Applications. IEEE Design & Test (Volume: 35, Issue: 1), Feb. 2018.
  32. Yu-Chih Chen, Brock Humphries, Riley Brien, Anne E. Gibbons, Yu-Ting Chen, Tonela Qyli, Henry R. Haley, Matthew E. Pirone, Benjamin Chiang, Annie Xiao, Yu-Heng Cheng, Yi Luan, Zhixiong Zhang, Jason Cong, Kathryn E. Luker, Gary D. Luker & Euisik Yoon. Functional Isolation of Tumor-Initiating Cells using Microfluidic-Based Migration Identifies Phosphatidylserine Decarboxylase as a Key Regulator. nature.com, Scientific Reports 8, Article number: 244, January 10, 2018.
  33. Yanghyo Kim, Wei-Han Cho, Yuan Du, Jason Cong, Tatsuo Itoh, and Mau-Chung Frank Chang. Impulse response analysis of carrier-modulated multiband RF-interconnect (MRFI). Analog Integrated Circuits and Signal Processing, pp 1-19, October 2017.
  34. Y. Chen, T. Nguyen, Y. Chen, S.T. Gurumani, Y. Liang, K. Rupnow, J. Cong, W.-M. Hwu, and D. Chen. FCUDA-HB: Hierarchical and Scalable Bus Architecture Generation on FPGAs With the FCUDA Flow. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 35, No.12, pp. 2032-2045, December 2016.
  35. D. Chen, J. Cong, S. Gurumani, W.-m. Hwu, K. Rupnow, and Z. Zhang . Platform Choices and Design Demands for IoT Platforms: Cost, Power, and Performance Tradeoffs. IET Cyber-Physical Systems: Theory & Applications, Issue 1, December, 2016.
  36. A. A. Del Barrio, J. Cong, and R. Hermida. A Distributed Clustered Architecture to Tackle Delay Variations in Datapath Synthesis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 35, no. 3, pp. 419-432, March 2016.
  37. J. Cong, P. Li, B. Xiao, and P. Zhang. An Optimal Microarchitecture for Stencil Computation Acceleration Based on Nonuniform Partitioning of Data Reuse Buffers. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 35, no. 3, pp. 407-418, March 2016.
  38. Young-kyu Choi and Jason Cong. Acceleration of EM-Based 3D CT Reconstruction Using FPGA. IEEE Transactions on Biomedical Circuits and Systems, Volume 10, No. 3, pp. 754-767, August 2015.
  39. S. Shen, A. Bui, J. Cong, and W. Hsu. An Automated Lung Segmentation Approach Using Bidirectional Chain Codes to Improve Nodule Detection Accuracy. Computers in Biology and Medicine, vol. 57, pp. 139-149, 2015.
  40. T. Wang, G. Sun, J. Chen, J. Gong, H. Wu, X. Li, S. Lu, and J. Cong. GRT: a Reconfigurable SDR Platform with High Performance and Usability. ACM SIGARCH Computer Architecture News (CAN), Volume 42 Issue 4, September 2014, pp. 51-56.
  41. Anpeng Huang, Wenyao Xu, Zhinan Li, Linzhen Xie, Majid Sarrafzadeh, Xiaoming Li, and Jason Cong. System Light-Loading Technology for mHealth: Manifold-Learning-Based Medical Data Cleansing and Clinical Trials in WE-CARE Project. IEEE Journal of Biomedical and Health Informatics, vol. 18, no. 5, pp. 1581-1589, September 2014.
  42. Jason Cong, Henry Duwe, Rakesh Kumar, and Sen Li. Better-Than-Worst-Case Design: Progress and Opportunities. Journal of Computer Science and Technology, 29(4): 656–663 July 2014.
  43. J. Cong, M. A. Ghodrat, M. Gill, B. Grigorian, G. Reinman. Architecture Support for Domain-Specific Accelerator-Rich CMPs. ACM Transactions on Embedded Computing Systems (TECS), Volume 13, Issue 4s, Article No. 131, April 2014.
  44. Y. Kim, L. Nan, J. Cong, M-C.F. Chang. High-Speed mm-Wave Data-Link Based on Hollow Plastic Cable and CMOS Transceiver. IEEE Microwave and Wireless Components Letters (MWCL), Volume 23, Issue 12, pp. 674-676, December 2013.
  45. Hugh T. Blair, Allan Wu and Jason Cong. Oscillatory neurocomputing with ring attractors: a network architecture for mapping locations in space onto patterns of neural synchrony. Philosophical Transactions of the Royal Society B 2014 369, 20120526, 23 December 2013.
  46. M. Yan, A. Bui, J. Cong and L.A. Vese. General Convergent Expectation Maximization (EM)-Type Algorithms for Image Reconstruction. Inverse Problems and Imaging, Volume 7, Issue 3, pp. 1007-1029, September 2013.
  47. J. Cong and B. Xiao. FPGA-RPI: A Novel FPGA Architecture With RRAM-Based Programmable Interconnects. IEEE Transaction on Very Large Scale Integration (VLSI) Systems, Volume PP, Issue 99, pp. 1-14, May 2013.
  48. G. Luo, Y. Shi and J. Cong. An Analytical Placement Framework for 3-D ICs and Its Extension on Thermal Awareness. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 32, Number 4, pp. 510-523, April 2013.
  49. A. Agarwal, J. Cong and B. Tagiku. The Survivability of Design-Specific Spare Placement in FPGA Architectures with High Defect Rates. ACM Transactions on Design Automation of Electronic Systems, Volume 18, Number 2, Article No. 33, March 2013.
  50. C. Xiao, M.F. Chang, J. Cong, M. Gill, Z. Huang, C. Liu, G. Reinman and H. Wu. Stream Arbitration: Towards Efficient Bandwidth Utilization for Emerging On-Chip Interconnects. ACM Transactions on Architecture and Code Optimization, Article No. 60, Volume 9, Number 4, January 2013.
  51. J. Chen, J. Cong, L.A. Vese, J. Villasensor, M. Yan and Y. Zou. A Hybrid Architecture for Compressive Sensing 3-D CT Reconstruction. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Volume 2, Issue 3, pp. 616-625, September 2012.
  52. K. Therdsteerasukdi, G. Byun, J. Ir, G. Reinman, J. Cong and M.F. Chang. Utilizing Radio-Frequency Interconnect for a Many-DIMM DRAM System. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Volume 2, Issue 2, pp. 210-227, June 2012.
  53. Y. Kim, S.-W. Tam, G.-S. Byun, H. Wu, L. Nan, G. Reinman, J. Cong and M.F. Chang. Analysis of Noncoherent ASK Modulation-Based RF-Interconnect for Memory Interface. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Volume 2, Issue 2, pp. 200-2-09, June 2012.
  54. J. Zhang, X. Liu, M. Tan, X. Cheng and J. Cong. Automatic Instruction-set Extension for Bitwise Operation-Intensive Applications. Chinese Journal of Electronics, Volume 40, Issue 2, pp. 209-214, February 2012.
  55. J. Cong, K. Gururaj, P. Zhang and Y. Zou. Task-level data model for hardware synthesis based on concurrent collections. Journal of Electrical and Computer Engineering - Special issue on ESL Design Methodology, Volume 2012, January 2012.
  56. K. Therdsteerasukdi, G.S. Byun, J. Cong, M.F. Chang and G. Reinman. Utilizing RF-I and Intelligent Scheduling for Better Throughput/Watt in a Mobile GPU Memory System. ACM's Transactions on Architecture and Code Optimization, Volume 8, Issue 4, Article 51, January 2012.
  57. J. Kim, H. Choi, S. Yoon, T. Bang, J. Park, C. Jung and J. Cong. An 8M Polygons/s 3-D Graphics SoC With Full Hardware Geometric and Rendering Engine for Mobile Applications. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 19, Number 8, pp. 1490-1495, August 2011.
  58. J. Cong, H. Huang, and W. Jiang. Pattern Mining for Behavioral Synthesis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 30, Issue 6, pp. 939-944, June 2011.
  59. J. Cong, B. Liu, S. Neuendorffer, J. Noguera, K. Vissers and Z. Zhang. High-Level Synthesis for FPGAs: From Prototyping to Deployment. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 30, Number 4, pp. 473-491, April 2011. (Keynote paper) .
  60. J. Cong, V. Sarkar, G. Reinman and A. Bui. Customizable Domain-Specific Computing. IEEE Design and Test of Computers, Volume 28, Number 2, pp. 5-15, March/April 2011.
  61. J. Cong, W. Jiang, B. Liu and Y. Zou. Automatic Memory Partitioning and Scheduling for Throughput and Power Optimization. ACM Transactions on Design Automation of Electronic Systems, Volume 16, Number 2, Article 15, pp. 1-25, March 2011. ACM (Best Paper Award).
  62. D. Chen, J. Cong, C. Dong, L. He, F. Li and C. Peng. Technology Mapping and Clustering for FPGA Architectures with Dual Supply Voltages. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 29, Number 11, pp. 1709-1721, November 2010.
  63. J. Cong, B. Liu, R. Majumdar and Z. Zhang. Behavior-Level Observability Analysis for Operation Gating in Low-Power Behavioral Synthesis. ACM Transactions on Design Automation of Electronic Systems, Volume 16, Number 1, Article 4, pp. 1-29, November 2010. (2012 Best Paper Award of the ACM Transactions on Design Automation of Electronic Systems) .
  64. J. Cong, J. Lee and P. Gupta. Evaluating Statistical Power Optimization. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 29, Number 11, pp. 1750-1762, November 2010.
  65. R. Brayton and J. Cong. NSF Workshop on EDA: Past, Present, and Future (Part 2). IEEE Design and Test of Computers, Volume 27, Number 3, pp. 62-74, May/June 2010.
  66. R. Brayton and J. Cong. NSF Workshop on EDA: Past, Present, and Future (Part 1). IEEE Design and Test of Computers, Volume 27, Number 2, pp. 68-74, March/April 2010.
  67. J. Cong and G. Luo. Advances and Challenges in 3D Physical Design. IPSJ Transactions on System LSI Design Methodology, Volume 3, pp. 2-18, Feburary 2010. (Invited paper).
  68. J. Cong, K. Gururaj, G. Han, and W. Jiang. Synthesis Algorithm for Application-Specific Homogeneous Processor Networks. IEEE Transaction on Very Large Scale Integration (VLSI) Systems, Volume 17, Number 9, pp.1318-1329, September 2009.
  69. J. Cong and Y. Zou. FPGA-Based Hardware Acceleration of Lithographic Aerial Image Simulation. ACM Transaction on Reconfigurable Technology and Systems, Volume 2, Number 3, pp.17:1-17:29, September 2009.
  70. Jason Cong and Wolfgang Rosenstiel. The Last Byte: The HLS tipping point. IEEE Design & Test, July 2009, DOI: 10.1109/MDT.2009.88.
  71. D. Chen, J. Cong, Y. Fan and L. Wan. LOPASS: A Low-Power Architectural Synthesis System for FPGAs With Interconnect Estimation and Optimization. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 18, Number 4, pp. 564-577, June 2009.
  72. J. Cong, Y. Fan, and J. Xu. Simultaneous Resource Binding and Interconnection Optimization Based on a Distributed Register-File Microarchitecture. ACM Transactions on Design Automation of Electronic Systems, Volume 14, Number 3, Article 35, pp.35:1-35:31, May 2009.
  73. J. Cong, G. Luo, and E. Radke. Highly Efficient Gradient Computation for Density-Constrained Analytical Placement. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 27, Number 12, pp. 2133-2144, December 2008.
  74. Y. Ma, Y. Liu, E. Kursun, G. Reinman, and J. Cong. Investigating the Effects of Fine-Grain Three-Dimensional Integration on Microarchitecture Design. Journal on Emerging Technologies in Computing Systems, Volume 4, Number 4, pp.17:1-17:30, October 2008.
  75. J. Cong and M. Xie. A Robust Mixed-Size Legalization and Detailed Placement Algorithm. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 27, Number 8, pp. 1349-1362, August 2008.
  76. J. Cong, G. Han, A. Jagannathan, G. Reinman, and K. Rutkowski. Accelerating Sequential Applications on CMPs Using Core Spilling. IEEE Transactions on Parallel and Distributed Systems, Volume 18, Number 8, pp. 1094- 1107, August 2007.
  77. C. Li, M. Xie, C. Koh, J. Cong and P. Madden. Routability-Driven Placement and White Space Allocation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 26, Number 5, pp. 858-871, May 2007.
  78. J. Cong and K. Minkovich. Optimality Study of Logic Synthesis for LUT-Based FPGAs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 26, Number 2, pp. 230-239, February 2007.
  79. D. Kirovski, Y.-Y. Hwang, M. Potkonjak and J. Cong. Protecting Combinational Logic Synthesis Solutions. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 25, Issue 12, pp. 2687-2696, Dec. 2006.
  80. D. Chen, J. Cong and P. Pan. FPGA Design Automation: A Survey. Foundations and Trends in Electronic Design Automation, vol. 1, no. 3, pp. 195-330, Nov 2006.
  81. J. Cong, G. Han and Z. Zhang. Architecture and Compiler Optimization for Data Bandwidth Improvement in Configurable Processors. IEEE Transaction on Very Large Scale Integration Systems, Volume 14, Number 9, pp. 986-997, Sept. 2006.
  82. J. Cong, M. Romesis and J.R. Shinnerl. Fast Floorplanning by Look-Ahead Enabled Recursive Bipartitioning. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 25, Issue 9, pp. 1719 - 1732, Sept. 2006.
  83. G. Chen and J. Cong. Simultaneous Placement with Clustering and Duplication. ACM Transaction on Design Automation of Electronic Systems, vol. 11, no. 3, pp. 740-772, July 2006.
  84. D. Chen, J. Cong, and J. Xu. Optimal Simultaneous Module and Multi-Voltage Assignment for Low Power. ACM Transaction on Design Automation of Electronic Systems, vol. 11, Issue 2, pp. 362-386, April 2006.
  85. F. Li, Y. Lin, L. He, D. Chen, and J. Cong. Power Modeling and Characteristics of Field Programmable Gate Arrays. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, Issue 11, pp. 1712-1724, November 2005.
  86. J. Cong, T. Kong, J. Shinnerl, M. Xie, and X. Yuan. Large Scale Circuit Placement. ACM Transaction on Design Automation of Electronic Systems, vol. 10, no. 2, pp. 389-430, April 2005.
  87. J. Cong, J. Fang, M. Xie, and Y. Zhang. MARS - A Multilevel Full-Chip Gridless Routing System. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 3, pp. 382-394, March 2005.
  88. J. Cong, H. Huang, and X. Yuan. Technology Mapping and Architecture Evaluation for k/m-Macrocell-based FPGAs. TODAES, vol. 10, pp. 3 - 23, January 2005 (2005 Best Paper Award of the ACM Transactions on Design Automation of Electronic Systems).
  89. J. Cong, and S. Lim. Retiming-based Timing Analysis With An Application to Mincut-based Global Placement. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 12, pp. 1684 - 1692, December 2004.
  90. J. Cong, Y. Fan, G. Han, X. Yang, and Z. Zhang. Architecture and Synthesis for On-Chip Multi-Cycle Communication. IEEE Transactions on Computer-Aided Design of Integrate d Circuits and Systems, Volume 23, Issue 4, pp.550-564, April 2004.
  91. C.-C. Chang, J. Cong, M. Romesis, and M. Xie. Optimality and Scalability Study of Existing Placement Algorithms. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp.537 - 549, April 2004.
  92. D. Chen, J. Cong, M. Ercegovac, and Z. Huang. Performance-driven Mapping for CPLD Architectures. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 10, pp. 1424-1431, October 2003.
  93. J. Cong, and S. K. Lim. Edge Separability-Based Circuit Clustering With Application to Multi-level Circuit Partitioning. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp . 346-357, July 2003.
  94. C.-C. Chang, J. Cong, D. Pan, and X. Yuan. Multilevel Global Placement with Congestion Control. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 4, pp. 395-409, April 2003 .
  95. T. Uchino and J. Cong. An Interconnect Energy Model Considering Coupling Effects. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 7, pp. 763-776, July 2002 .
  96. J. Cong and Z. Pan. Wire Width Planning For Interconnect Performance Optimization. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 3, pp.319-329, March 2002. .
  97. J. Cong, T. Kong and Z. Pan. Buffer Block Planning for Interconnect Planning and Prediction. IEEE Transactions on Very Large Scale Integration, vol. 9, no. 6, pp.929-937, December 2001.
  98. J. Cong, C. K. Koh and P. H. Madden. Interconnect layout Optimization Under Higher Order RLC Model for MCM Designs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 12, pp.1455-1463, December 2001 .
  99. J. Cong, L. He, C. K. Koh and Z. Pan. Interconnect Sizing and Spacing with Consideration of Coupling Capacitance. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 9, pp.1164-1169, September 2001.
  100. J. Cong and Y. -Y. Hwang. Boolean Matching for LUT-Based Logic Blocks With Applications to Architecture Evaluation and Technology Mapping. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 9, pp.1077-1090, September 2001.
  101. J. Cong and Z. (D.) Pan. Interconnect Performance Estimation Models for Design Planning. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 739--752, vol. 20, no. 6, June 2001.
  102. J. Cong, J. Fang and K. -Y. Khoo. DUNE - A Multilayer Gridless Routing System. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, (no. 5), pp 633-647, May 2001.
  103. C.-C. Chang and J. Cong. Pseudopin Assignment with Crosstalk Noise Control. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 5, pp. 598-611, May 2001.
  104. J. Cong. An Interconnect-Centric Design Flow for Nanometer Technologies. Proceedings of the IEEE, vol. 89, No. 4, pp 505-528, April 2001.
  105. J. Cong and S. Xu. Performance-Driven Technology Mapping for Heterogeneous FPGAs. IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, vol. 19, no. 11, pp. 1268-1281, November 2000.
  106. J. Cong and Y. Hwang. Structural Gate Decomposition for Depth-Optimal Technology in LUT-based FPGA Designs. ACM Trans. on Design Automation of Electronic Systems, vol. 5, no. 2, pp. 193-225, April 2000.
  107. J. Cong, J. Fang and K.Y. Khoo. Via design rule consideration in multi-layer maze routing algorithms. IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, vol. 19, no. 2, pp 215-223, February 2000.
  108. J. Cong and C. Wu. Optimal FPGA Mapping and Retiming with Efficient Initial State Computation. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 11, pp 1595 -1607, November 1999.
  109. C.-C. Chang and J. Cong. An Efficient Approach To Multilayer Layer Assignment With An Application To Via Minimization. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.18, no. 5, p.608-620, May 1999.
  110. J. Cong and L. He. Theory and Algorithm of Local-Refinement-Based Optimization with Application to Device and Interconnect Sizing. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.18, no.4, pp. 406-420, April 1999.
  111. J. Cong, A. B. Kahng and K.-S. Leung. Efficient Algorithms for the Minimum Shortest Path Steiner Arborescence Problem with Applications to VLSI Physical Design. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.17, no. 1, pp. 24-39, January 1999.
  112. J. Cong, A. B. Kahng, C. K. Koh and C.-W. Albert Tsao. Bounded-Skew Clock and Steiner Routing. ACM Trans. on Design Automation of Electronic Systems, vol. 3, pp. 341-388, 1998.
  113. J. Cong and C. Wu. An Efficient Algorithm for Performance Optimal FPGA Technology Mapping with Retiming. IEEE Trans. on Computer-Aided Design of Integrated Circuits And Systems vol. 17, no. 9, pp. 738-748, 1998.
  114. J. Cong and P. Madden. Performance-Driven Routing with Multiple Sources. IEEE Trans. on Computer-Aided Design, vol. 16, pp. 410-419, April 1997.
  115. T.C. Lee and J. Cong. The New Line in IC Design. IEEE Spectrum, pp. 52-58, March 1997.
  116. J. Cong and L. He. Optimal Wiresizing for Interconnects with Multiple Sources. ACM Transaction on Design Automation of Electronic Systems, vol. 1, no. 4, pp. 478-511, October 1996.
  117. J. Cong, L. He, C. K. Koh and P. Madden. Performance Optimization of VLSI Interconnect Layout. Integration, the VLSI Journal, vol. 21, pp. 1-94, 1996.
  118. L. Kleinrock, M. Gerla, N. Bambos, J. Cong, E. Gafni, L. Bergman, J. Bannister, S. Monacos, T. Bujewski, P. C. Hu, B. Kannan, B. Kwan, E. Leonardi, J. Peck, P. Palnati, and S. Walton. The Supercomputer Supernet Testbed: A WDM-Based Supercomputer Interconnect. Journal of Lightwave Technology, vol. 14, no. 6, pp. 1388-1399, June 1996.
  119. J. Cong, W. J. Labio, and N. Shivkumar. Multiway VLSI Circuit Partitioning Based on Dual net Representation. IEEE Trans. on Computer-Aided Design, vol. 15, no. 4, pp. 396-409, April 1996.
  120. J. Cong and Y. Ding. Combinational Logic Synthesis for LUT Based Field Programmable Gate Arrays. ACM Trans. on Design Automation of Electronic Systems, vol. 1, no. 2, pp. 145-204 April 1996.
  121. J. Cong and K. Y. Khoo. An Efficient Multilayer MCM Router Based on Four-Via Routing. IEEE Trans. on Computer-Aided Design, vol. 14, no. 10, pp. 1277-1290, October 1995.
  122. J. Cong and K. S. Leung. Optimal Wiresizing Under Elmore Delay Model. IEEE Trans. on Computer-Aided Design, vol. 14, no. 3, pp. 321-336, Mar. 1995.
  123. L. Kleinrock, M. Gerla, N. Bambos, J. Cong, E. Gafni, L. Bergman, and J. Bannister. The Supercomputer Supernet: A Scalable Distributed Terabit Network. Journal of High Speed Networks, vol. 4, no. 4, pp. 407-424, 1995 .
  124. J. Cong and C. K. Koh. Simultaneous Driver and Wire Sizing for Performance and Power Optimization. IEEE Trans. on VLSI Systems, vol. 2, no. 4, pp. 408-425, December 1994.
  125. J. Cong, Y. Ding, T. Gao and K. C. Chen. LUT-Based FPGA Technology Mapping Under Arbitrary Net-Delay Model. Computers and Graphics, vol. 18, no. 4, pp. 507-516, 1994.
  126. Y. Cai, D. F. Wong and J. Cong. Channel Density Minimization by Pin Permutation. VLSI Design: An International Journal of Custom-Chip Design, Simulation, and Testing (Special Issue on Optimization in VLSI Synthesis and Layout), vol. 2, no. 2, pp. 171-183, 1994.
  127. C. J. Alpert, J. Cong, A. B. Kahng, G. Robins and M. Sarrafzadeh. On the Minimum Density Interconnection Tree Problem. VLSI Design: An International Journal of Custom-Chip Design, Simulation, and Testing (Special Issue on Optimization in VLSI Synthesis and Layout), vol. 2, no. 2, pp. 171-183, 1994.
  128. J. Cong and Y. Ding. On Nominal Delay Minimization in LUT-Based FPGA Technology Mapping. Integration: the VLSI Journal, vol. 18, pp. 507-516, 1994.
  129. J. Cong and Y. Ding. On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping. IEEE Trans. on VLSI Systems, vol. 2, no. 2, pp. 137-148, June 1994.
  130. D. Zhou, S. Su, F. Fsui, D. S Gao, and J. Cong. A Simplified Synthesis of Transmission Lines with a Tree Structure. Journal of Analog Integrated Circuits and Signal Processing (Special Issue on High-Speed Interconnects), vol. 5, no. 1, pp. 19-30, January 1994.
  131. J. Cong and Y. Ding. FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs. IEEE Trans. on Computer-Aided Design, vol. 13, no. 1, pp. 1-12, January 1994. (1995 Circuit and System Society Best Paper Award in IEEE Transactions on CAD). (Induction to FPGA and Reconfigurable Computing Hall of Fame 2017) .
  132. J. Cong, A. B. Kahng and G. Robins. Matching-Based Methods for High-Performance Clock Routing. IEEE Trans. on Computer-Aided Design, vol. 12, no. 8, pp. 1157-1169, August 1993.
  133. J. Cong, B. Preas and C. L. Liu. Physical Models and Efficient Algorithms for Over-the-Cell Routing in Standard Cell Designs. IEEE Trans. on Computer-Aided Design, vol. 12, no. 5, pp. 723-734, May 1993.
  134. J. Cong, M. Hossain and N. Sherwani. A Provably Good Multilayer Topological Planar Routing Algorithm In IC Layout Designs. IEEE Trans. on Computer-Aided Design, vol. 12, no. 1, pp. 70-78, January 1993.
  135. K. Y. Khoo and J. Cong. A Fast Multilayer General Area Router for MCM Designs. IEEE Trans. on Circuits & Systems II - Analog & Digital Signal Processing,, vol. 39, no. 11, pp. 841-851, November 1992.
  136. J. Cong and B. Preas. A New Algorithm for Standard Cell Global Routing. Integration: the VLSI Journal, vol. 14, no. 1, pp. 49-65, November 1992.
  137. K. C. Chen, J. Cong, Y. Ding, A. Kahng, and P. Trajmar. DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization. IEEE Design & Test of Computers, vol. 9, no. 3, pp. 7-20, September, 1992.
  138. J. Cong, A. Kahng, G. Robins, M. Sarrafzadeh and C. K. Wong. Provably Good Performance-Driven Global Routing. IEEE Trans. on Computer-Aided Design, vol. 11, no. 6, pp. 739-752, June 1992.
  139. J. Cong. Pin Assignment with Global Routing for General Cell Design. IEEE Trans. on Computer-Aided Design, vol. 10, pp. 1401-1412, November 1991.
  140. J. Cong and C. L. Liu. On the k-Layer Planar Subset and Topological Via Minimization Problems. IEEE Trans. on Computer-Aided Design, Vol. 10, pp. 972-981, August 1991.
  141. K. S. The, D. F. Wong and J. Cong. A Layout Modification Approach to Via Minimization. IEEE Trans. on Computer-Aided Design, vol. 10, pp. 536-541, April 1991.
  142. J. Cong and C. L. Liu. Over-the-Cell Channel Routing. IEEE Trans. Computer-Aided Design, vol. 9, pp. 408-418, April 1990. (1992 IEEE CAS Outstanding Young Author Award Candidate) .
  143. J. Cong and D. F. Wong. Generating More Compactable Channel Routing Solutions. Integration: the VLSI Journal, vol. 9, pp 199-214, April 1990.
  144. J. Cong, D. F. Wong and C. L. Liu. A New Approach to Three- or Four-Layer Channel Routing. IEEE Trans. Computer-Aided Design, vol. 7, pp 1094-1104, July 1988.

Conference publications

  1. Atefeh Sohrabizadeh, Wan-Hsuan Lin, Daniel Bochen Tan, Madelyn Cain, Sheng-Tao Wang, Mikhail D. Lukin. GNN-Based Performance Prediction of Quantum Optimization of Maximum Independent Set. 2024 International Conference on Computer-Aided Design (ICCAD), Special Session Paper, October 27-31, 2024, New Jersey, USA.
  2. Hanyu Wang, Daniel Bochen Tan, Jason Cong. Quantum State Preparation Circuit Optimization Exploiting Dont Cares. Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design (ICCAD '24). October 27-31, 2024, New Jersey, USA.
  3. Yunsheng Bai, Atefeh Sohrabizadeh, Zijian Ding, Rongjian Liang, Weikai Li, Ding Wang, Haoxing Ren, Yizhou Sun, Jason Cong. Learning to Compare Hardware Designs for High-Level Synthesis. 2024 ACM/IEEE International Symposium on Machine Learning for CAD (MLCAD '24), September 9–11, 2024, Salt Lake City, UT, USA. ACM, New York, NY, USA, 7 pages. Also available on arXiv2409.13138, http://arxiv.org/abs/2409.13138.
  4. Zongyue Qin[1], Yunsheng Bai, Atefeh Sohrabizadeh, Zijian Ding, Ziniu Hu, Yizhou Sun, Jason Cong. Cross-Modality Program Representation Learning for Electronic Design Automation with High-Level Synthesis. ACM/IEEE International Symposium on Machine Learning for CAD (MLCAD ’24), September 9–11, 2024, Salt Lake City, UT, USA. ACM, New York, NY, USA, 12 pages.
  5. Hanrui Wang, Pengyu Liu, Daniel Bochen Tan, Yilian Liu, Jiaqi Gu, David Z. Pan, Jason Cong, Umut A. Acar, Song Han. Atomique: A Quantum Compiler for Reconfigurable Neutral Atom Arrays. Proceedings of the 2024 International Symposium on Computer Architecture (ISCA), June 29-July 3, 2024, Buenos Aires, Argentina.
  6. Hanrui Wang, Daniel Bochen Tan, Pengyu Liu, Yilian Liu, Jiaqi Gu, Jason Cong, Song Han. Q-Pilot: Field Programmable Qubit Array Compilation with Flying Ancillas. Proceedings of the 61st ACM/IEEE Design Automation Conference (DAC), June 23-27, 2024, San Francisco, CA.
  7. Neha Prakriya, Yuze Chi, Suhail Basalama, Linghao Song, Jason Cong. TAPA-CS: Enabling Scalable Accelerator Design on Distributed HBM-FPGAs. ASPLOS '24: Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 3, pp 966-980, April 2024.
  8. Daniel Bochen Tan, Shuohao Ping, Jason Cong. Depth-Optimal Addressing of 2D Qubit Array with 1D Controls Based on Exact Binary Matrix Factorization. 2024 Design, Automation and Test in Europe Conference (DATE), March 25-27, 2024, Valencia, Spain.
  9. Zifan He, Linghao Song, Robert F. Lucas, Jason Cong. LevelST: Stream-based Accelerator for Sparse Triangular Solver. In Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA ’24), March 3–5, 2024, Monterey, CA.
  10. Yunsheng Bai, Atefeh Sohrabizadeh, Zongyue Qin, Ziniu Hu, Yizhou Sun, and Jason Cong. Towards a Comprehensive Benchmark for High-Level Synthesis Targeted to FPGAs. Thirty-seventh Conference on Neural Information Processing Systems (NeurIPS) Datasets and Benchmarks Track, 2023.
  11. Atefeh Sohrabizadeh, Yunsheng Bai, Yizhou Sun, Jason Cong. Robust GNN-based Representation Learning for HLS. In Proceedings of the 42nd IEEE/ACM International Conference on Computer-Aided Design (ICCAD '23) - Best Paper Award candidate.
  12. Jason Cong. Lightning Talk: Scaling Up Quantum Compilation – Challenges and Opportunities. Proceedings of the 60th ACM/IEEE Design Automation Conference (DAC), July 9-13, 2023, San Francisco, CA, DOI: 10.1109/DAC56929.2023.10247677.
  13. Suhail Basalama, Jie Wang, Jason Cong. A Comprehensive Automated Exploration Framework for Systolic Array Designs. Proceedings of the 60th ACM/IEEE Design Automation Conference (DAC), July 9-13, 2023, San Francisco, CA, 6 pages.
  14. Wan-Hsuan Lin, Jason Kimko, Bochen Tan, Nikolaj Bjørner, Jason Cong. Scalable Optimal Layout Synthesis for NISQ Quantum Processors. Proceedings of the 60th ACM/IEEE Design Automation Conference (DAC), July 9-13, 2023, San Francisco, CA, 6 pages.
  15. Neha Prakriya, Yu Yang, Baharan Mirzasoleiman, Cho-Jui Hsieh, Jason Cong. NeSSA: Near-Storage Data Selection for Accelerated Machine Learning Training. HotStorage ’23: Proceedings of the 15th ACM Workshop on Hot Topics in Storage and File Systems, July 2023, Boston, MA. ACM, New York, NY, pp 8-15.
  16. Moazin Khatti, Xingyu Tian, Yuze Chi, Licheng Guo, Jason Cong and Zhenman Fang. PASTA: Programming and Automation Support for Scalable Task-Parallel HLS Programs on Modern Multi-Die FPGAs. 2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), May 8-11, 2023, Marina Del Rey, CA, pp 12-22.
  17. Linghao Song, Licheng Guo, Suhail Basalama, Yuze Chi, Robert F. Lucas, and Jason Cong. Callipepla: Stream Centric Instruction Set and Mixed Precision for Accelerating Conjugate Gradient Solver. Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA '23). ACM, New York, NY, USA, pp 247–258, February 2023.
  18. Jinming Zhuang, Jason Lau, Hanchen Ye, Zhuoping Yang, Yubo Du, Jack Lo, Kristof Denolf, Stephen Neuendorffer, Alex Jones, Jingtong Hu, Deming Chen, Jason Cong, Peipei Zhou.. CHARM: Composing Heterogeneous Accelerators for Matrix Multiply on Versal ACAP Architecture. Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA ’23), February 12–14, 2023, Monterey, CA, USA. ACM, New York, NY, USA, 12 pages. https://doi.org/10.1145/3543622.3573210.
  19. Bochen Tan, Dolev Bluvstein, Mikhail D. Lukin, and Jason Cong. Qubit Mapping for Reconfigurable Atom Array. In Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design (ICCAD '22). Association for Computing Machinery, New York, NY, USA, Article 107, pp 1–9, October 2022.
  20. Sihao Liu , Jian Weng , Dylan Kupsh, Atefeh Sohrabizadeh , Zhengrong Wang , Licheng Guo, Jiuyang Liu, Maxim Zhulin, Rishabh Mani, Lucheng Zhang, Jason Cong, Tony Nowatzki. OverGen: Improving FPGA Usability through Domain-specific Overlay Generation. The 55th IEEE/ACM International Symposium on Microarchitecture (MICRO 2022), Chicago, IL, October 1-5, 2022 (Best Paper Nominee).
  21. Y. Wu, F. V. Mutlu, Y. Liu, E. Yeh, R. Liu, C. Iordache, J. Balcas, H. Newman, R. Sirvinskas, M. Lo, S. Song, J. Cong, L. Zhang, S. Timilsina, S. Shannigrahi, C. Fan, D. Pesavento, J. Shi, L. Benmohamed. N-DISE: NDN-based Data Distribution for Large-Scale Data-Intensive Science. The 9th ACM Conference on Information Centric Networking (ICN 2022), September 19-21, 2022, Osaka, Japan.
  22. Yunsheng Bai, Atefeh Sohrabizadeh, Yizhou Sun, and Jason Cong. Improving GNN-Based Accelerator Design Automation with Meta Learning. Proceedings of the 59th ACM/IEEE Design Automation Conference (DAC), July 10–14, 2022, San Francisco, CA, USA,1347-1350.
  23. Atefeh Sohrabizadeh, Yunsheng Bai, Yizhou Sun, and Jason Cong. Automated Accelerator Optimization Aided by Graph Neural Networks. Proceedings of the 59th ACM/IEEE Design Automation Conference (DAC), July 10–14, 2022, San Francisco, CA, USA, pp 55-60.
  24. Linghao Song, Yuze Chi, Licheng Guo, and Jason Cong. Serpens: A High Bandwidth Memory Based Accelerator for General-Purpose Sparse Matrix-Vector Multiplication. Proceedings of the 59th ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, July 10–14, 2022, pp 211-216.
  25. Zhe Chen, Jim Zhou, Garrett J. Blair, Hugh T. Blair, and Jason Cong. Efficient Kernels for Real-Time Position Decoding from In Vivo Calcium Images. The IEEE Symposium on Circuits and Systems (ISCAS), May 28-June 1, 2022.
  26. Linghao Song, Yuze Chi, and Jason Cong. Pyxis: An Open-Source Performance Dataset of Sparse Accelerators. IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), May 22-27, 2022, pp 76-80. DOI: 10.1109/ICASSP43922.2022.9746473.
  27. Atefeh Sohrabizadeh, Yuze Chi, Jason Cong. StreamGCN: Accelerating Graph Convolutional Networks with Streaming Processing. 2022 IEEE Custom Integrated Circuits Conference (CICC), April 2022, pp 1-8. DOI: 10.1109/CICC53496.2022.9772832.
  28. Yuze Chi, Licheng Guo, and Jason Cong. Accelerating SSSP for Power-Law Graphs. Proceedings of the 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA ’22), February 27-March 1, 2022, Virtual Event, CA, USA. ACM, New York, NY, USA, pp 190-200, DOI: 10.1145/3490422.3502358.
  29. Licheng Guo, Pongstorn Maidee, Yun Zhou, Chris Lavin, Jie Wang, Yuze Chi, Weikang Qiao, Alireza Kaviani, Zhiru Zhang, and Jason Cong. RapidStream: Parallel Physical Implementation of FPGA HLS Designs. Proceedings of the 2022 ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA ’22), February 27–March 1, 2022, Virtual Event, USA. ACM, New York, NY, USA, pp 1-12, DOI: 10.1145/3490422.3502361. (Best Paper Award) .
  30. Linghao Song, Yuze Chi, Atefeh Sohrabizadeh, Young-kyu Choi, Jason Lau, and Jason Cong. Sextans: A Streaming Accelerator for General-Purpose Sparse-Matrix Dense-Matrix Multiplication. Proceedings of the 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA '22), February 2022. Association for Computing Machinery, New York, NY, USA, pp 65–77. DOI: 10.1145/3490422.3502357.
  31. Bochen Tan and Jason Cong. Optimal Qubit Mapping with Simultaneous Gate Absorption. ICCAD Special Session Paper, 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD'21), DOI: 10.1109/ICCAD51958.2021.9643554.
  32. Saranyu Chattopadhyay, Florian Lonsing, Luca Piccolboni, Deepraj Soni, Peng Wei, Xiaofan Zhang, Yuan Zhou, Luca Carloni, Deming Chen, Jason Cong, Ramesh Karri, Zhiru Zhang, Caroline Trippel, Clark Barrett and Subhasish Mitra. Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition. Formal Methods in Computer-Aided Design 2021 (FMCAD), Hybrid Conference, Yale University, New Haven, Connecticut, pp 42-52, DOI: 10.34727/2021/isbn.978-3-85448-046-4_12, October 20-22, 2021.
  33. Zhe Chen, Garrett J. Blair, Hugh T. Blair, Jason Cong. Fast Calcium Trace Extraction for Large-Field-of-View Miniscope. 2021 IEEE Biomedical Circuits and Systems Conference (BioCAS), October 6-9, 2021, DOI: 10.1109/BioCAS49922.2021.9644936.
  34. Zhe Chen, Garrett J. Blair, Changliang Guo, Daniel Aharoni, Hugh T. Blair, Jason Cong. Live Demonstration: Real-Time Calcium Trace Extraction from Large-Field-of-View Miniscope. The 2021 IEEE Biomedical Circuits and Systems Conference (BioCAS), October 6-9, 2021, DOI: 10.1109/BioCAS49922.2021.9645015.
  35. Liqiang Lu, Naiqing Guan, Yuyue Wang, Liancheng Jia, Zizhang Luo, Jieming Yin, Jason Cong, Yun Liang. TENET: A Framework for Modeling Tensor Dataflow Based on Relation-centric Notation. Proceedings of the ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA 2021), Virtual Event, June 14-19, 2021, pp 720-733, DOI 10.1109/ISCA52012.2021.00062.
  36. Yuze Chi, Licheng Guo, Jason Lau, Young-kyu Choi, Jie Wang, and Jason Cong. Extending High-Level Synthesis for Task-Parallel Programs. Proceedings of the 29th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM’21), Virtual Event, May 9-12, 2021, pp 204-213, DOI: 10.1109/FCCM51124.2021.00032.
  37. Weikang Qiao, Jihun Oh, Licheng Guo, Mau-Chung Frank Chang, Jason Cong. FANS: FPGA-Accelerated Near-Storage Sorting. Proceedings of the 29th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM’21), Virtual Event, May 9-12, 2021, pp 106-114, DOI 10.1109/FCCM51124.2021.00020.
  38. Peipei Zhou, Jiayi Sheng, Cody Hao Yu, Peng Wei, Jie Wang, Di Wu, Jason Cong . MOCHA: Multinode Cost Optimization in Heterogeneous Clouds with Accelerators.. Proceedings of the 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA ’21), February 28-March 2, 2021, Virtual Event. ACM, New York, NY, USA, pp 273-279, DOI: 10.1145/3431920.3439304.
  39. Jie Wang, Licheng Guo, and Jason Cong. AutoSA: A Polyhedral Compiler for High-Performance Systolic Arrays on FPGA. Proceedings of the 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA ’21), February 28-March 2, 2021, Virtual Event, ACM, New York, NY, USA, pp 93-104, DOI: 10.1145/3431920.3439292.
  40. Young-kyu Choi, Yuze Chi, Weikang Qiao, Nikola Samardzic, and Jason Cong. HBM Connect: High-Performance HLS Interconnect for FPGA HBM. Proceedings of the 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA ’21), February 28-March 2, 2021, Virtual Event, pp 116-126, DOI: 10.1145/3431920.343930.
  41. Licheng Guo, Yuze Chi, Jie Wang, Jason Lau, Weikang Qiao, Ecenur Ustun, Zhiru Zhang, Jason Cong. AutoBridge: Coupling Coarse-Grained Floorplanning and Pipelining for High-Frequency HLS Design on Multi-Die FPGAs. Proceedings of the 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA ’21), February 28–March 2, 2021, Virtual Event. ACM, New York, NY, USA, pp 81-92. DOI: 10.1145/3431920.3439289 (Best Paper Award).
  42. Bochen Tan and Jason Cong. Optimal Layout Synthesis for Quantum Computing. Proceedings of the 2020 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Article 137, pp 1-9, November 2-5, 2020. DOI: 10.1145/3400302.3415620.
  43. Zhe Chen, Garrett J. Blair, Hugh T. Blair, Jason Cong. BLINK: Bit-Sparse LSTM Inference Kernel Enabling Efficient Calcium Trace Extraction for Neurofeedback Devices. Proc. ACM/IEEE Int. Symp. on Low Power Electronics and Design (ISLPED'20), pp. 217-222, Aug. 2020. DOI: 10.1145/3370748.3406552.
  44. Eshan Singh, Florian Lonsing, Saranyu Chattopadhyay, Maxwell Strange, Peng Wei, Xiaofan Zhang, Yuan Zhou, Deming Chen, Jason Cong, Priyanka Raina, Zhiru Zhang Clark Barrett and Subhasish Mitra. A-QED Verification of Hardware Accelerators. Proceedings of the 57th Design Automation Conference (DAC 2020), Article No. 14, pp 1-6, July 19-23, 2020. DOI: 10.1109/DAC18072.2020.9218715.
  45. Yuze Chi and Jason Cong. Exploiting Computation Reuse for Stencil Accelerators. Proceedings of the 57th Design Automation Conference (DAC 2020), San Francisco, CA, July 19-23, 2020, DOI: 10.1109/DAC18072.2020.9218680.
  46. Licheng Guo*, Jason Lau*, Yuze Chi, Jie Wang, Cody Hao Yu, Zhe Chen, Zhiru Zhang, and Jason Cong. Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency. Proceedings of the 57th Design Automation Conference (DAC 2020), San Francisco, CA, July 19-23, 2020, DOI: 10.1109/DAC18072.2020.9218718. (Best Paper Nominee).
  47. Nikola Samardzic*, Weikang Qiao*, Vaibhav Aggarwal, Mau-Chung Frank Chang, Jason Cong. Bonsai: High-Performance Adaptive Merge Tree Sorting. Proceedings of the 47th International Symposium on Computer Architecture (ISCA 2020), May 30-June 3, 2020, pp 282-294, DOI: 10.1109/ISCA45697.2020.00033.
  48. Jason Lau*, Aishwarya Sivaraman*, Qian Zhang*, Muhammad Ali Gulzar, Jason Cong, Miryung Kim. HeteroRefactor: Refactoring for Heterogeneous Computing with FPGA. Proceedings of 42nd International Conference on Software Engineering, Seoul, Republic of Korea, May 23–29, 2020, pp 493-505, DOI: 10.1145/3377811.3380340.(* equal co-first authors in alphabetical order).
  49. Michael Lo, Zhenman Fang, Jie Wang, Peipei Zhou, Mau-Chung Frank Chang and Jason Cong. Algorithm-Hardware Co-design for BQSR Acceleration in Genome Analysis ToolKit. The 28th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM’20), Fayetteville, Arkansas, May 3-6, 2020, pp 157-166, DOI: 10.1109/FCCM48280.2020.00029.
  50. Atefeh Sohrabizadeh, Jie Wang, and Jason Cong. End-to-End Optimization of Deep Learning Applications. The 28th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA ’20), Seaside, CA, February 23–25, 2020, pp 133–139, DOI: 10.1145/3373087.3375321.
  51. Jiajie Li, Yuze Chi, and Jason Cong. HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration. The 28th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA ’20), Seaside, CA, February 23–25, 2020, pp 51–57, DOI 10.1145/3373087.3375320.
  52. Zhenyuan Ruan, Tong He, Jason Cong. Analyzing and Modeling In-Storage Computing Workloads On EISC — An FPGA-Based System-Level Emulation Platform. Proceedings of the IEEE/ACM International Conference Computer Aided Design (ICCAD), November 2019, DOI: 10.1109/ICCAD45719.2019.8942135. (Best Paper Award).
  53. Zhenman Fang, Farnoosh Javadi, Jason Cong and Glenn Reinman. Understanding Performance Gains of Accelerator-rich Architectures. The 30th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) July 15-17, 2019. Cornell Tech, NY, pp 239-246, DOI: 10.1109/ASAP.2019.00013. (Invited Paper).
  54. Zhenyuan Ruan, Tong He, and Jason Cong. INSIDER: Designing In-Storage Computing System for Emerging High-Performance Drive. 2019 USENIX Annual Technical Conference (ATC), Renton, WA, July 10-12, 2019.
  55. Xuechao Wei, Yun Liang, Jason Cong. Overcoming Data Transfer Bottlenecks in FPGA-based DNN Accelerators via Layer Conscious Memory Management. Proceedings of the 56th Design Automation Conference (DAC 2019), Las Vegas, NV, June 2-6, 2019, Article No. 125, pp 1–6, DOI: 10.1145/3316781.3317875.
  56. Jiaxi Zhang, Wentai Zhang, Guojie Luo, Xuechao Wei, Yun Liang, and Jason Cong. Frequency Improvement of Systolic Array-Based CNNs on FPGAs. The 2019 IEEE International Symposium on Circuits and Systems, Sapporo, Japan, May 26-29, 2019, DOI: 10.1109/ISCAS.2019.8702071.
  57. Weikang Qiao, Jieqiong Du, Zhenman Fang, Michael Lo, Mau-Chung Frank Chang, Jason Cong. An FPGA-based BWT Accelerator for Bzip2 Data Compression. The 27th IEEE International Symposium On Field-Programmable Custom Computing Machines, San Diego, CA, April 28-May 1, 2019, pp 96-99, DOI: 10.1109/FCCM.2019.00023.
  58. Licheng Guo*, Jason Lau*, Zhenyuan Ruan, Peng Wei, and Jason Cong. Hardware Acceleration of Long Read Pairwise Overlapping in Genome Sequencing: A Race Between FPGA and GPU. The 27th IEEE International Symposium on Field-Programmable Custom Computing Machines, San Diego, CA, April 28-May 1, 2019, pp 127-135, DOI: 10.1109/FCCM.2019.00027.
  59. Yi-Hsiang Lai, Yuze Chi, Yuwei Hu, Jie Wang, Cody Hao Yu, Yuan Zhou, Jason Cong, and Zhiru Zhang. HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computing. The 27th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays held in Seaside, CA, February 24-26, 2019, Pages 242–251, DOI: 10.1145/3289602.3293910. (Best Paper Award) .
  60. Zhe Chen, Hugh T. Blair, and Jason Cong. LANMC: LSTM-Assisted Non-Rigid Motion Correction on FPGA for Calcium Image Stabilization. Proc. ACM/SIGDA Int. Symp. Field-Programmable Gate Arrays (FPGA’19), Feb. 2019, pp 104–109, DOI: 10.1145/3289602.3293919.
  61. Yuze Chi, Young-kyu Choi, Jason Cong, and Jie Wang. Rapid Cycle-Accurate Simulator for High-Level Synthesis. Proc. ACM/SIGDA Int. Symp. Field-Programmable Gate Arrays (FPGA’19), Feb. 2019, pp. 178-183, DOI: 10.1145/3289602.3293918.
  62. Xuechao Wei, Yun Liang, Xiuhong Li, Cody Hao Yu, Peng Zhang, and Jason Cong . TGPA: Tile-Grained Pipeline Architecture for Low Latency CNN Inference. Proceedings of the IEEE/ACM International Conference Computer Aided Design (ICCAD), November 2018.
  63. Zhenyuan Ruan, Tong He, Jason Cong. Unleash The Performance of Emerging Storage via Reconfigurable Drive Controller. OSDI'18 Poster.
  64. Jason Cong, Jie Wang. PolySA: Polyhedral-Based Systolic Array Auto-Compilation. Proceedings of the IEEE/ACM International Conference Computer Aided Design (ICCAD), November 2018.
  65. Yuze Chi, Jason Cong, Peng Wei, and Peipei Zhou. SODA: Stencil with Optimized Dataflow Architecture. Proceedings of the IEEE/ACM International Conference Computer Aided Design (ICCAD), November 2018 (Best Paper Nominee).
  66. Y. Choi and J. Cong. HLS-Based Optimization and Design Space Exploration for Applications with Variable Loop Bounds. Proceedings of the IEEE/ACM International Conference Computer Aided Design (ICCAD), November 2018.
  67. Li M, Shen S, Gao W, Hsu W, Cong J. Computed tomography image enhancement using 3D convolutional neural network. The 4th Workshop on Deep Learning in Medical Image Analysis, Granada, Spain, September 2018.
  68. Jason Cong, Licheng Guo, Po-Tsang Huang, Peng Wei and Tianhe Yu. SMEM++: A Pipelined and Time-Multiplexed SMEM Seeding Accelerator for Genome Sequencing. The 28th International Conference on Field-Programmable Logic and Applications (FPL 18). August 27-31, 2018, Dublin, Ireland.
  69. Zhe Chen, Hugh T. Blair, Andrew Howe, Jason Cong. CLINK: Compact LSTM Inference Kernel for Energy Efficient Neurofeedback Devices. Proc. ACM/IEEE Int. Symp. on Low Power Electronics and Design (ISLPED'18), Seattle, WA, July 23-25, 2018. (Best Paper Award).
  70. Jason Cong, Peng Wei and Cody Hao Yu. From JVM to FPGA: Bridging Abstraction Hierarchy via Optimized Deep Pipelining. The 10th USENIX Workshop on Hot Topics in Cloud Computing (HotCloud 18), Boston, MA, July 9, 2018.
  71. Cody Hao Yu, Peng Wei, Max Grossman, Peng Zhang, Vivek Sarkar, Jason Cong. S2FA: An Accelerator Automation Framework for Heterogeneous Computing in Datacenters. Proceedings of the 55rd Annual Design Automation Conference (DAC), San Francisco, CA, June 24-28, 2018.
  72. Jason Cong, Peng Wei, Cody Hao Yu, Peng Zhang. Automated Accelerator Generation and Optimization with Composable, Parallel and Pipeline Architecture. Proceedings of the 55rd Annual Design Automation Conference (DAC), San Francisco, CA, June 24-28, 2018. DOI# 10.1145/3195970.3195999.
  73. Jason Cong, Peng Wei, Cody Hao Yu, Peipei Zhou. Latte: Locality Aware Transformation for High-Level Synthesis. The 26th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines, Boulder, CO, April 29-May 1, 2018.
  74. Zhenyuan Ruan, Tong He, Bojie Li, Peipei Zhou, and Jason Cong. ST-Accel: A High-Level Programming Platform for Streaming Applications on FPGA. The 26th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines, Boulder, CO, April 29-May 1, 2018.
  75. Weikang Qiao, Jieqiong Du, Zhenman Fang, Michael Lo, Mau-Chung Frank Chang, Jason Cong. High-Throughput Lossless Compression on Tightly Coupled CPU-FPGA Platforms. The 26th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines, Boulder, CO, April 29-May 1, 2018.
  76. Jason Cong, Zhenman Fang, Michael Lo, Hanrui Wang, Jingxian Xu and Shaochong Zhang. Understanding Performance Differences of FPGAs and GPUs. The 26th IEEE International Symposium on Field-Programmable Custom Computing Machines, Boulder, CO, April 29-May 1, 2018.
  77. Peipei Zhou, Zhenyuan Ruan, Zhenman Fang, Megan Shand, David Roazen, Jason Cong . Doppio: I/O-Aware Performance Analysis, Modeling and Optimization for In-Memory Computing Framework. 2018 IEEE International Symposium on Performance Analysis of Systems and Software, Belfast, United Kingdom, April 2-4, 2018 (Best Paper Nominee).
  78. Peng Wang, Shuo Li, Guangyu Sun, Xiaoyang Wang, Yiran Chen, Hai (Helen) Li, Jason Cong, Nong Xiao, and Tao Zhang. RC-NVM: Enabling Symmetric Row and Column Memory Accesses for In-Memory Databases. HPCA 2018: 24th IEEE International Symposium on High-Performance Computer Architecture, Vienna, Austria, Feb 24-28, 2018.
  79. Yanghyo Kim, Boyu Hu, Yuan Du, Adrian Tang, Huan-Neng Chen, Chewnpu Jou, Jason Cong, Tatsuo Itoh, Mau-Chung Frank Chang. A 20Gb/s 79.5mW 127GHz CMOS Transceiver with Digitally Pre-Distorted PAM-4 Modulation for Contactless Communications. 2018 IEEE International Solid-State Circuits Conference, San Francisco, CA, February 11-15, 2018.
  80. Y. Choi, P. Zhang, P. Li, and J. Cong. HLScope+: Fast and Accurate Performance Estimation for FPGA HLS. IEEE/ACM Int. Conf. Computer Aided Design (ICCAD), Nov. 2017. DOI# 10.1109/ICCAD.2017.8203844 .
  81. Jason Cong, Zhenman Fang, Farnoosh Javadi, and Glenn Reinman. AIM: Accelerating Computational Genomics through Scalable and Noninvasive Accelerator-Interposed Memory. International Symposium on Memory Systems (MEMSYS), Oct 2017, (Best Paper Award).
  82. Jason Cong, Peng Wei, Cody Hao Yu, and Peipei Zhou. Bandwidth Optimization Through On-Chip Buffer Restructuring for HLS. Proceedings of the 54rd Annual Design Automation Conference (DAC 2017), Austin, TX, June 18-22, 2017.
  83. Xuechao Wei, Cody Hao Yu, Peng Zhang, Youxiang Chen, Yuxin Wang, Han Hu, Yun Liang, and Jason Cong. Automated Systolic Array Architecture Synthesis for High Throughput CNN Inference on FPGAs. Proceedings of the 54rd Annual Design Automation Conference (DAC 2017), Austin, TX, June 18-22, 2017. (Best Paper Nominee).
  84. Yanghyo Kim, Yuan Du, Adrian Tang, Yan Zhao, Brian Lee, Huan-Neng Chen, Chewnpu Jou, Jason Cong, Tatsuo Itoh, and Mau-Chung Frank Chang. A 125 GHz Transceiver in 65 nm CMOS Assembled With FR4 PCB Antenna for Contactless Wave-Connectors. The 2017 International Microwave Symposium (IMS'17), Honolulu, Hawaii, June 4-9, 2017.
  85. J. Wang, X. Xie and J. Cong, . Communication Optimization on GPU: A Case Study of Sequence Alignment Algorithms. 2017 IEEE International Parallel and Distributed Processing Symposium (IPDPS), Orlando, FL, May 29-June 2, 2017, pp. 72-81.
  86. Young-kyu Choi and Jason Cong. HLScope: High-Level Performance Debugging for FPGA Designs. The 25th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM'17), Napa, CA, April 30-May 2, 2017.
  87. Yijin Guan, Hao Liang, Ningyi Xu, Wenqiang Wang, Shaoshuai Shi, Xi Chen, Guangyu Sun, Wei Zhang, and Jason Cong. FP-DNN: An Automated Framework for Mapping Deep Neural Networks onto FPGAs with RTL-HLS Hybrid Templates. The 25th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM'17), Napa, CA, April 30-May 2, 2017.
  88. Jason Cong, Zhenman Fang, Yuchen Hao, and Glenn Reinman. Supporting Address Translation for Accelerator-Centric Architectures. The 23rd IEEE Symposium on High Performance Computer Architecture (HPCA 2017 Best Paper Nominee), 2017.
  89. X. Wei, Y. Liang, T. Wang, S. Lu, and J. Cong. Throughput Optimization for Streaming Applications on CPU-FPGA Heterogeneous Systems. The 22nd Asia and South Pacific Design Automation Conference (ASPDAC 2017), Chiba/Tokyo, Japan, January 16-19, 2017.
  90. Y. Guan, Z. Yuan, G. Sun, and J. Cong. FPGA-based Accelerator for Long Short-Term Memory Recurrent Neural Networks. The 22nd Asia and South Pacific Design Automation Conference (ASPDAC 2017), Chiba/Tokyo, Japan, January 16-19, 2017.
  91. Franck Cappello, Kazutomo Yoshii, Hal Finkel, and Jason Cong. Re-form: FPGA-powered true codesign flow for high-performance computing in the post-Moore era. The 2016 Post-Moore’s Era Supercomputing (PMES) Workshop, Salt Lake City, Utah, November 14, 2016.
  92. Chen Zhang, Zhenman Fang, Peipei Zhou, Peichen Pan, Jason Cong. Caffeine: Towards Uniformed Representation and Acceleration for Deep Convolutional Neural Networks. Proceedings of the 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD 2016), November 2016. (2019 TCAD Donald O. Pederson Best Paper Award).
  93. Muhuan Huang, Di Wu, Cody Hao Yu, Zhenman Fang, Matteo Interlandi, Tyson Condie, and Jason Cong. Programming and Runtime Support to Blaze FPGA Accelerator Deployment at Datacenter Scale. Proceedings of the Seventh ACM Symposium on Cloud Computing (SoCC 2016), Santa Clara, CA, October 5-7, 2016.
  94. Chen Zhang, Di Wu, Jiayu Sun, Guangyu Sun, Guojie Luo and Jason Cong. Energy-Efficient CNN Implementation on a Deeply Pipelined FPGA Cluster. International Symposium on Low Power Electronics and Design (ISLPED), August 8-10, 2016.
  95. Yu-Ting Chen, Jason Cong, Zhenman Fang, Jie Lei and Peng Wei. When Apache Spark Meets FPGAs: A Case Study for Next-Generation DNA Sequencing Acceleration. The 8th USENIX Workshop on Hot Topics in Cloud Computing (Hot Cloud '16), Denver, CO, June 20-21, 2016.
  96. Jason Cong, Muhuan Huang, Di Wu, and Cody Hao Yu. Heterogeneous Datacenters: Options and Opportunities. Proceedings of the 53rd Annual Design Automation Conference (DAC 2016), Austin, TX, June 5-9, 2016 (Invited Paper).
  97. Young-kyu Choi, Jason Cong, Zhenman Fang, Yuchen Hao, Glenn Reinman, and Peng Wei. A Quantitative Analysis on Microarchitectures of Modern CPU-FPGA Platforms. Proceedings of the 53rd Annual Design Automation Conference (DAC 2016), Austin, TX, June 5-9, 2016.
  98. Peipei Zhou, Hyunseok Park, Zhenman Fang, Jason Cong, Andre DeHon. Energy Efficiency of Full Pipelining: A Case Study for Matrix Multiplication. The 24th IEEE International Symposium on Field-Programmable Custom Computing Machines, Washington DC, May 1-3, 2016.
  99. Mau-Chung Frank Chang, Yu-Ting Chen, Jason Cong, Po-Tsang Huang, Chun-Liang Kuo and Cody Hao Yu. The SMEM Seeding Algorithm Acceleration for DNA Sequence Alignment. The 24th IEEE International Symposium on Field-Programmable Custom Computing Machines, Washington DC, May 1-3, 2016.
  100. Jason Cong, Muhuan Huang, Peichen Pan, Di Wu, Peng Zhang. Software infrastructure for enabling FPGA-based accelerations in data centers. Proceedings of the 2016 International Symposium on Low Power Electronics and Design. August 2016.
  101. Guojie Luo, Wentai Zhang, Jiaxi Zhang, and Jason Cong. Scaling Up Physical Design: Challenges and Opportunities. International Symposium on Physical Design (ISPD) 2016, Santa Rosa, CA, April 3-6, 2016.
  102. Deming Chen, Jason Cong, Swathi Gurumani, Wen-mei Hwu, Kyle Rupnow, and Zhiru Zhang. System Synthesis and Automated Verification: Design Demands for IoT Devices. The 2016 Sensors to Cloud Architectures Workshop (SCAW 2016), Barcelona, Spain, March 2016.
  103. Jason Cong, Hui Huang, and Mohammad Ali Ghodrat. A Scalable Communication-Aware Compilation Flow for Programmable Accelerators. ASPDAC 2016, Macau, China, Jan 25-28, 2016.
  104. Jason Cong, and Cody Hao Yu. Impact of Loop Transformations on Software Reliability. The 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD 2015), Austin, Texas, November 2015.
  105. Jason Cong, Zhenman Fang, Michael Gill, and Glenn Reinman. PARADE: A Cycle-Accurate Full System Simulation Platform for Accelerator-Rich Architectural Design and Exploration. The 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD 2015), Austin, Texas, November 2015.
  106. Yu-Ting Chen, Jason Cong, Sen Li, Myron Peto, Paul Spellman, Peng Wei, and Peipei Zhou. CS-BWAMEM: A fast and scalable read aligner at the cloud scale for whole genome sequencing. High Throughput Sequencing Algorithms and Applications (HITSEQ) Poster Session Dublin, Ireland, July 2015. Best Poster Award.
  107. Peng Wang, Le Cao, Chunbo Lai, Leqi Zou, Guangyu Sun, and Jason Cong. InterFS: An Interplanted Distributed File System to Improve Storage Utilization. The 2015 Asia-Pacific Workshop on Systems (APSys),Tokyo, Japan, July 27-28, 2015 .
  108. Yu-Ting Chen and Jason Cong. Interconnect Synthesis of Heterogeneous Accelerators in a Shared Memory Architecture. The 2015 International Symposium on Low Power Electronics and Design (ISLPED), Rome, Italy, July 22-24, 2015 .
  109. Peng Zhang, Muhuan Huang, Bingjun Xiao, Hui Huang, and Jason Cong. CMOST: A System-Level FPGA Compilation Framework. Design Automation Conference (DAC) 2015, San Francisco, CA, June 7-11, 2015.
  110. Jason Cong, Michael Gill, Yuchen Hao, Glenn Reinman, and Bo Yuan. On-chip Interconnection Network for Accelerator-Rich Architectures. Design Automation Conference (DAC) 2015, San Francisco, CA, June 7-11, 2015.
  111. C. Lai, S. Jiang, L. Yang, S. Lin, G. Sun, Z. Hou, C. Cui, and J. Cong. Atlas: Baidu’s Key-value Storage System for Cloud Data. MSST 2015: 31st Symposium on Mass Storage Systems and Technologies, Santa Clara, CA, June 1-5, 2015.
  112. Yu-Ting Chen, Jason Cong, Jie Lei, and Peng Wei. A Novel High-Throughput Acceleration Engine for Read Alignment. The 23rd Annual IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM '15), Vancouver, British Columbia, Canada, May 2015 .
  113. Yu-Ting Chen, Jason Cong, and Bingjun Xiao. ARACompiler: A Prototyping Flow and Evaluation Framework for Accelerator-Rich Architectures. 2015 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Philadelphia, PA, March 29-31, 2015.
  114. Chen Zhang, Peng Li, Guangyu Sun, Yijin Guan, Bingjun Xiao, Jason Cong. Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks. 23rd International Symposium on Field-Programmable Gate Arrays (FPGA2015).
  115. Peng Li, Peng Zhang, Louis-Noël Pouchet, Jason Cong. Resource-Aware Throughput Optimization for High-Level Synthesis. 23rd International Symposium on Field-Programmable Gate Arrays (FPGA2015).
  116. M. Li, P. Zhang, C. Zhu, H. Jia, X. Xie, J. Cong, and W. Gao. High Efficiency VLSI Implementation of an Edge-directed Video Up-scaler Using High Level Synthesis. The 2015 IEEE International Conference on Consumer Electronics, Las Vegas, NV, January 2015.
  117. Jason Cong and Bingjun Xiao. Minimizing Computation in Convolutional Neural Networks. Proceedings of the 24th International Conference on Artificial Neural Networks, Hamburg, Germany, September 2014.
  118. Muhuan Huang, Kevin Lim and Jason Cong. A Scalable, High-Performance Customized Priority Queue. Proceedings of the 24th International Conference on Field Programmable Logic and Applications (FPL 2014), Munich, Germany, September 2-4, 2014.
  119. Jian Gong, Tao Wang, Jiahua Chen, Haoyang Wu, Fan Ye, Songwu Lu and Jason Cong. An Efficient and Flexible Host-FPGA PCIe Communication Library. Proceedings of the 24th International Conference on Field Programmable Logic and Applications (FPL 2014), Munich, Germany, September 2-4, 2014.
  120. Jason Cong, Peng Li , Bingjun Xiao, and Peng Zhang. An Optimal Microarchitecture for Stencil Computation Acceleration Based on Non-Uniform Partitioning of Data Reuse Buffers. Design Automation Conference, 2014.
  121. Jason Cong, Mohammad Ali Ghodrat, Michael Gill, Beayna Grigorian, Karthik Gururaj, Glenn Reinman. Accelerator-Rich Architectures: Opportunities and Progresses. Design Automation Conference (DAC 2014).
  122. T. Wang, G. Sun, J. Chen, J. Gong, H. Wu, X. Li, S. Lu and J. Cong. GRT: A Reconfigurable SDR Platform with High Performance and Usability. Proceedings of the 5th International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies (HEART 2014), Sendai Miyagi, Japan, June 2014.
  123. Jason Cong, Hui Huang, Chiyuan Ma, Bingjun Xiao and Peipei Zhou. A Fully Pipelined and Dynamically Composable Architecture of CGRA. Proceedings of the 22nd IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), Boston, Massachusetts, May 2014.
  124. Young-kyu Choi, Jason Cong, and Di Wu. FPGA Implementation of EM Algorithm for 3D CT Reconstruction. Proceedings of the 22nd IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), Boston, Massachusetts, May 2014.
  125. J.Cong, S. Jiang, S. Lin, J. Ouyang, G. Sun, P. Wang, C. Zhang. An Efficient Design and Implementation of LSM-Tree based Key-Value Store on Open-Channel SSD. Proceedings of the 2014 EuroSys Conference in Amsterdam, Netherlands, April 2014.
  126. Jason Cong. From Design to Design Automation. Proceedings of the The International Symposium on Physical Design (ISPD 2014), March 2014.
  127. Jason Cong, Muhuan Huang, Peng Zhang. Combining computation and communication optimizations in system synthesis for streaming applications. International Symposium on Field-Programmable Gate Arrays, FPGA 2014.
  128. Yuxin Wang, Peng Li, Jason Cong. Theory and Algorithm for Generalized Memory Partitioning in High-Level Synthesis. International Symposium on Field-Programmable Gate Arrays, FPGA 2014.
  129. J. Cong and B. Xiao. Optimization of Interconnects Between Accelerators and Shared Memories in Dark Silicon. Proceedings of the 2013 International Conference on Computer-Aided Design (ICCAD 2013), pp. 630-637, November 2013.
  130. H.T. Blair, J. Cong, D. Wu. FPGA Simulation Engine for Customized Construction of Neural Microcircuit. Proceedings of the 2013 International Conference on Computer-Aided Design (ICCAD 2013), pp. 607-614, November 2013.
  131. W. Zuo, P. Li, D. Chen, L-N. Pouchet, S. Zhong and J. Cong. Improving Polyhedral Code Generation for High-Level Synthesis. Proceedings of the International Conference on Hardware/Software Co-design and System Synthesis (CODES+ISSS 2013), pp. 1-10, September-October 2013 (Best Paper Award).
  132. Yu-Ting Chen, Jason Cong, Mohammad Ali Ghodrat, Muhuan Huang, Chunyue Liu, Bingjun Xiao, Yi Zou. Accelerator-rich CMPs: From concept to real hardware. International Conference on Computer Design (ICCD) 2013.
  133. J. Cong, M. Ercegovac, M. Huang, S. Li and B. Xiao. Energy-Efficient Computing Using Adaptive Table Lookup Based on Nonvolatile Memories. Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED 2013), pp. 280 - 285, September 2013.
  134. J. Cong, M.A. Ghodrat, M. Gill, B. Grigorian, H. Huang and G. Reinman. Composable Accelerator-rich Microprocessor Enhanced for Adaptivity and Longevity. Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED 2013), pp. 305-310, September 2013.
  135. J. Cong and B. Xiao. Defect Tolerance in Nanodevice-based Programmable Interconnects: Utilization Beyond Avoidance. Proceedings of the 50th Annual Design Automation Conference (DAC 2013), Austin, TX, Article 9, May-June 2013.
  136. A. Papakonstantinou, D. Chen, W-M. Hu, J. Cong and Y. Liang. Throughput-Oriented Kernel Porting onto FPGAs. Proceedings of the 50th Annual Design Automation Conference (DAC 2013), Austin, TX, Article 11, May-June 2013.
  137. Y. Wang, P. Li, P. Zhang, C. Zhang and J. Cong. Memory Partitioning for Multidimensional Arrays in High-Level Synthesis. Proceedings of the 50th Annual Design Automation Conference (DAC 2013), Austin, TX, Article 12, May-June 2013.
  138. P. Wang, G. Sun, T. Wang, Y. Xie and J. Cong. Designing Scratchpad Memory Architecture with Emerging STT-RAM Memory Technologies. Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS 2013), Beijing, China, May 2013.
  139. L.-N. Pouchet, P. Zhang, P. Sadayappan and J. Cong. Polyhedral-Based Data Reuse Optimization for Configurable Computing. Proceedings of the 21st ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2013), Monterey, California, pp. 29-38, February 2013(Best Paper Award).
  140. Z. Wei, Y. Liang, K. Rupnow, P. Li, D. Chen and J. Cong. Improving High Level Synthesis Optimization Opportunity through Polyhedral Transformations. Proceedings of the 21st ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2013), Monterey, California, pp. 9-18, February 2013.
  141. J. Cong and K. Gururaj. Architecture Support for Custom Instructions with Memory Operations. Proceedings of the 21st ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2013), Monterey, California, pp. 231-234, February 2013.
  142. C. Xiao, M.F. Chang, J. Cong, M. Gill, Z. Huang, C. Liu, G. Reinman and H. Wu. Stream Arbitration: Towards Efficient Bandwidth Utilization for Emerging On-Chip Interconnects. Proceedings of the 8th International Conference on High Performance Embedded Architectures & Compilers (HiPEAC 2013), Berlin, Germany, January 2013.
  143. J. Cong, G. Luo, K. Tsota and B. Xiao. Optimizing Routability in Large-Scale Mixed-Size Placement. Proceedings of the 18th Asia and South Pacific Design Automation Conference (ASPDAC 2013), Yokohama, Japan, January 2013. (The ASP-DAC 2023 Ten-Year Retrospective Most Influential Paper Award).
  144. P. Li, Y. Wang, P. Zhang, G. Luo, T. Wang and J. Cong. Memory Partitioning and Scheduling Co-optimization in Behavioral Synthesis. Proceedings of the 2012 International Conference on Computer-Aided Design (ICCAD 2012), San Jose, California, pp. 488-495, November 2012.
  145. H. Wu, L. Nan, S.-W. Tam, H.-H. Hsieh, C. Jou, G. Reinman, J. Cong, and M.-C. F. Chang. A 60GHz On-Chip RF-Interconnect with λ/4 Coupler for 5Gbps Bi-Directional Communication and Multi-Drop Arbitration. Proceedings of IEEE Custom Integrated Circuits Conference (CICC 2012), San Jose, California, September 2012.
  146. J. Cong, M.A. Ghodrat, M. Gill, B. Grigorian and G. Reinman. CHARM: A Composable Heterogeneous Accelerator-Rich Microprocessor. Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED 2012), Redondo, California, pp. 379-384, July-August 2012.
  147. J. Cong and B. Yuan. Energy-Efficient Scheduling on Heterogeneous Multi-core Architectures. Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED 2012), Redondo, California, pp. 345-350, July-August 2012.
  148. Y. Chen, J. Cong, H. Huang, C. Liu, R. Prabhakar and G. Reinman. Static and Dynamic Co-Optimizations for Blocks Mapping in Hybrid Caches. Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED 2012), Redondo, California, pp. 237-242, July-August 2012.
  149. J. Cong, M.A. Ghodrat, M. Gill, C. Liu and G. Reinman. BiN: A Buffer-in-NUCA Scheme for Accelerator-Rich CMPs. Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED 2012), Redondo, California, pp. 225-230, July-August 2012.
  150. J. Cong, M.A. Ghodrat, M. Gill, B. Grigorian and G. Reinman. Architecture Support for Accelerator-Rich CMPs. Proceedings of the 49th Annual Design Automation Conference (DAC 2012), San Francisco, CA, pp. 843-849, June 2012.
  151. A. Sbirlea, Y. Zou, Z. Budimlic, J. Cong and V. Sarkar. Mapping a data-flow programming model onto heterogeneous platforms. Proceedings of the 13th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, Tools and Theory for Embedded Systems (LCTES 2012), Beijing, China, pp. 61-70, June 2012.
  152. J. Cong and B. Liu. A Metric for Layout-Friendly Microarchitecture Optimization in High-Level Synthesis. Proceedings of the 49th Annual Design Automation Conference (DAC 2012), San Francisco, CA, pp. 1239-1244, June 2012.
  153. J. Cong, P. Zhang and Y. Zou. Optimizing Memory Hierarchy Allocation with Loop Transformations for High-Level Synthesis. Proceedings of the 49th Annual Design Automation Conference (DAC 2012), San Francisco, CA, pp. 1233-1238, June 2012.
  154. J. Cong, B. Liu, G. Luo and R. Prabhakar. Towards Layout-Friendly High-Level Synthesis. Proceedings of the International Symposium on Physical Design (ISPD 2012), Napa, CA, pp. 165-172, March 2012 (Invited paper).
  155. J. Cong. Transformation from Ad Hoc EDA to Algorithmic EDA. Proceedings of the International Symposium on Physical Design (ISPD 2012), Napa, CA, pp. 57-62, March 2012 (Invited paper).
  156. J. Cong, M. Huang, B. Liu, P. Zhang and Y. Zou. Combining Module Selection and Replication for Throughput-Driven Streaming Programs. Proceedings of Design, Automation and Test in Europe (DATE 2012), Dresden, Germany, March 2012.
  157. Y. Chen, J. Cong, H. Huang, B. Liu, C. Liu, M. Potkonjak and G. Reinman. Dynamically Reconfigurable Hybrid Cache: An Energy-Efficient Last-Level Cache Design. Proceedings of Design, Automation and Test in Europe (DATE 2012), Dresden, Germany, March 2012.
  158. Y. Kim, G. Byun, A. Tang, C.P. Jou, H.H. Hsieh, G. Reinman, J. Cong and M. F. Chang. An 8Gb/s/pin 4pJ/b/pin Single-T-Line Dual (Base+RF) Band Simultaneous Bidirectional Mobile Memory I/O Interface with Inter-Channel Interference Suppression. IEEE International Solid-State Circuits Conference Digest of Technical papers (ISSCC 2012), San Francisco, CA, pp. 50-52, February 2012.
  159. J. Chen, J. Cong, M. Yan and Y. Zou. FPGA-Accelerated 3D Reconstruction using Compressive Sensing. Proceedings of the 20th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2012), Monterey, CA, pp. 163-166, February 2012.
  160. J. Cong, M.A. Ghodrat, M. Gill, H. Huang, B. Liu, R. Prabhakar, G. Reinman and M. Vitanza. Compilation and Architecture Support for Customized Vector Instruction Extension. Proceedings of the 17th Asia and South Pacific Design Automation Conference (ASPDAC 2012), Sydney, Australia, pp. 652-657, January 2012 (Invited paper).
  161. Y. Wang, P. Zhang, X. Cheng and J. Cong. An Integrated and Automated Memory Optimization Flow for FPGA Behavioral Synthesis. Proceedings of the 17th Asia and South Pacific Design Automation Conference (ASPDAC 2012), Sydney, Australia, pp. 257-262, January 2012.
  162. A. Bui, K. Cheng, J. Cong, L. Vese, Y. Wang, B. Yuan and Y. Zou. Platform Characterization for Domain-Specific Computing. Proceedings of the 17th Asia and South Pacific Design Automation Conference (ASPDAC 2012), Sydney, Australia, pp. 94-99, January 2012 (Invited paper).
  163. K. Therdsteerasukdi, G. Byun, J. Cong, M.F. Chang and G. Reinman. Utilizing RF-I and Intelligent Scheduling for Better Throughput/Watt in a Mobile GPU Memory System. Proceedings of the 7th International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC 2012), Paris, France, January 2012.
  164. J. Cong, Y. Huang and B. Yuan. ATree-Based Topology Synthesis for On-Chip Network. Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD 2011), San Jose, CA, pp. 651-658, November 2011.
  165. J. Cong, P. Zhang and Y. Zou. Combined Loop Transformation and Hierarchy Allocation for Data Reuse Optimization. Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD 2011), San Jose, CA, pp. 185-192, November 2011.
  166. J. Cong and K. Gururaj. Assuring Application-Level Correctness against Soft Errors. Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD 2011), San Jose, CA, pp. 150-157, November 2011.
  167. K. Therdsteerasukdi, G. Byun, J. Ir, G. Reinman, J. Cong and M.F. Chang. The DIMM Tree Architecture: A High Bandwidth and Scalable Memory System. Proceedings of the 2011 IEEE International Conference on Computer Design (ICCD 2011), Amherst, Massachusetts, pp. 388-395, October 2011.
  168. Y. Ming, J. Chen, L.A. Vese, J. Villasenor, A. Bui, and J. Cong. EM+TV Based Reconstruction for Cone-Beam CT with Reduced Radiation. Proceedings of the 7th International Symposium on Visual Computing, Las Vegas, Nevada, pp. 1-10, September 2011 (Lecture Notes in Computer Science, Volume 6938, pp. 1-10).
  169. Y. Chen, J. Cong and G. Reinman. HC-Sim: A Fast and Exact L1 Cache Simulator with Scratchpad Memory Co-Simulation Support. Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2011), Taipei, Taiwan, pp. 295-304, October 2011.
  170. J. Cong, B. Grigorian, G. Reinman and M. Vitanza. Accelerating Vision and Navigation Applications on a Customizable Platform. Proceedings of the 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2011), Santa Monica, CA, pp. 25-32, September 2011.
  171. J. Cong, M. Huang and Y. Zou. Accelerating Fluid Registration Algorithm on Multi-FPGA Platforms. Proceedings of the 21st International Conference on Field Programmable Logic and Applications (FPL 2011), Chania, Crete, Greece, pp. 50-57, September 2011.
  172. J. Cong, K. Gururaj, M. Huang, S. Li, B. Xiao and Y. Zou. Domain-Specific Processor with 3D Integration for Medical Image Processing. Proceedings of the 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2011), Santa Monica, CA, pp. 247-250, September 2011.
  173. J. Cong, K. Gururaj, H. Huang, C. Liu, G. Reinman and Y. Zou. An Energy-Efficient Adaptive Hybrid Cache. Proceedings of International Symposium on Low Power Electronics and Design (ISLPED 2011), Fukuoka, Japan, pp. 67-72, August 2011.
  174. J. Chen, M. Yan, L.A. Vese, J. Villasenor, A. Bui and J. Cong. EM+TV for Reconstruction of Cone-Beam CT with Curved Detectors Using GPU. Proceedings of International Meeting on Fully Three-Dimensional Image Reconstruction in Radiology and Nuclear Medicine, Potsdam, Germany, pp. 363-366, July 2011.
  175. J. Cong, G. Luo and Y. Shi. Thermal-Aware Cell and Through-Silicon-Via Co-Placement for 3D ICs. Proceedings of the 48th Annual Design Automation Conference (DAC 2011), San Diego, CA, pp. 405-410, June 2011.
  176. J. Cong, M. Huang and Y. Zou. 3D Recursive Gaussian IIR on GPU and FPGAs, A Case Study for Accelerating Bandwidth-Bounded Applications. Proceedings of the 9th IEEE Symposium on Application Specific Processors (SASP 2011), San Diego, CA, pp. 70-73, June 2011.
  177. J. Cong and B. Xiao. mrFPGA: A Novel FPGA Architecture with Memristor-Based Reconfiguration. Proceedings of the 7th IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2011), San Diego, CA, pp. 1-8, June 2011.
  178. J. Cong, H. Huang, C. Liu and Y. Zou. A Reuse-Aware Prefetching Scheme for Scratchpad Memory. Proceedings of the 48th Annual Design Automation Conference (DAC 2011), San Diego, CA, pp. 960-965, June 2011.
  179. J. Cong, J. Lee, and G. Luo. A Unified Optimization Framework for Simultaneous Gate Sizing and Placement under Density Constraints. Proceedings of the 24th IEEE International Symposium on Circuits and Systems (ISCAS 2011), Rio de Janeiro, Brazil, pp. 1207-1210, May 2011.
  180. A. Papakonstantinou, Y. Liang, J.A. Stratton, K. Gururaj, D. Chen, W.M. Hwu and J. Cong. Multilevel Granularity Parallelism Synthesis on FPGAs. Proceedings of 19th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2011), Salt Lake City, UT, pp. 178-185, May 2011. (Best Paper Award).
  181. G-S. Byun, Y. Kim, J. Kim, S-W Tam, H-H. Hsieh, P-Y. Wu, C. Jou, J. Cong, G. Reinman and M-C. F. Chang. An 8.4Gb/s 2.5pJ/b Mobile Memory I/O Interface Using Simultaneous Bidirectional Dual (Base+RF) Band Signaling. IEEE International Solid-State Circuits Conference Digest of Technical papers (ISSCC 2011), San Francisco, CA, pp. 488-490, February 2011.
  182. J. Cong, M. A. Ghodrat, M. Gill, C. Liu, G. Reinman and Y. Zou. AXR-CMP: Architecture Support in Accelerator-Rich CMPs. Proceedings of the 2nd Workshop on SoC Architecture, Accelerators and Workloads (SAW-2) , San Antonio, TX, pp. 19-26, February 2011.
  183. T. Thorolfsson, G. Luo, J. Cong and P D. Franzon. Logic-on-Logic 3D Integration and Placement. Proceedings of the 2nd IEEE International 3D System Integration Conference (3DIC 2010) , Munich, Germany, November 2010.
  184. J. Cong and K. Minkovich. LUT-Based FPGA Technology Mapping for Reliability. Proceedings of the 47th Annual Design Automation Conference (DAC 2010) , Anaheim, CA, pp. 517-522, June 2010.
  185. J. Cong, C. Liu and G. Reinman. ACES: Application-Specific Cycle Elimination and Splitting for Deadlock-Free Routing on Irregular Network-on-Chip. Proceedings of the 47th Annual Design Automation Conference (DAC 2010) , Anaheim, CA, pp. 443-448, June 2010.
  186. J. Cong and Y. Zou. A Comparative Study on the Architecture Templates for Dynamic Nested Loops. Proceedings of the 18th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2010) , Charlotte, NC, pp.251-254, May 2010.
  187. J. Cong and G. Luo. An Analytical Placer for Mixed-size 3D Placement. Proceedings of the International Symposium on Physical Design (ISPD 2010), San Francisco, CA, pp. 61-66, March 2010.
  188. J. Cong, B. Liu, and J. Xu. Coordinated Resource Optimization for Behavioral Synthesis. Proceedings of Design, Automation and Test Europe (DATE 2010), Dresden, Germany, pp. 1267-1272, March 2010.
  189. J. Cong, H. Huang, and W. Jiang. A Generalized Control-Flow-Aware Pattern Recognition Algorithm for Behavior Synthesis. Proceedings of Design, Automation and Test Europe (DATE 2010), Dresden, Germany, pp. 1255-1260, March 2010.
  190. J. Cong, K. Gururaj, W. Jiang, B. Liu, K. Minkovich, B. Yuan and Y. Zou. Accelerating Monte Carlo based SSTA using FPGA. Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA 2010), Monterey, California, pp. 111-114, February 2010.
  191. J. Zhang, Z. Zhang, S. Zhou, M. Tan, X. Liu, X. Cheng and J. Cong. Bit-Level Optimization for High-Level Synthesis and FPGA-Based Acceleration. Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA 2010), Monterey, California, pp. 59-68, February 2010.
  192. J. Cong, and Y. Zou. Parallel Multi-level Analytical Global Placement on Graphics Processing Units. Proceedings of the 2009 International Conference on Computer-Aided Design(ICCAD 2009), San Jose, California, pp. 681-688, November 2009.
  193. T. F. Chan, J. Cong, and E. Radke. A Rigorous Framework for Convergent Net Weighting Schemes in Timing-Driven Placement. Proceedings of the 2009 International Conference on Computer-Aided Design(ICCAD 2009), San Jose, California, pp. 288-294, November 2009.
  194. J. Cong, B. Liu, and Z. Zhang. Scheduling with Soft Constraints. Proceedings of the 2009 International Conference on Computer-Aided Design(ICCAD 2009), San Jose, California, pp. 47-54, November 2009.
  195. J. Cong, W. Jiang, B. Liu, and Y. Zou. Automatic Memory Partitioning and Scheduling for Throughput and Power Optimization. Proceedings of the 2009 International Conference on Computer-Aided Design(ICCAD 2009), San Jose, California, pp. 697-704, November 2009.
  196. J. Cong, A. Liu, and B. Liu. A Variation-Tolerant Scheduler for Better Than Worst-Case Behavioral Synthesis. Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2009), Grenoble, France, pp. 221-228, October 2009.
  197. S-B. Lee, S.-W. Tam, I. Pefkianakis, S. Lu, M. F. Chang, C. Guo, G. Reinman, C. Peng, M. Naik, L. Zhang, and J. Cong. A Scalable Micro Wireless Interconnect Structure for CMPs. ACM MobiCom 2009, Beijing, China, pp. 217-228, September 2009.
  198. J. Zhang, Z. Zhang, S. Zhou, M. Tan, X. Liu, X. Cheng, and J. Cong. Bit-Level Transformation and Optimization for Hardware Synthesis of Algorithmic Descriptions. Proceedings of the 18th International Workshop on Logic & Synthesis (IWLS 2009), Berkeley, California, pp. 119-126, July 31-August 2, 2009.
  199. J. Cong, A. Liu, and B. Liu. A Variation-Tolerant Scheduler for Better Than Worst-Case Behavioral Synthesis. Proceedings of the 18th International Workshop on Logic & Synthesis (IWLS 2009), Berkeley, California, pp. 72-79, July 31-August 2, 2009.
  200. J. Cong, B. Liu, and Z. Zhang. Behavior-Level Observability Dont-Cares and Application to Low-Power Behavioral Synthesis. Proceedings of the International Symposium on Low Power Electronics & Design (ISLPED 2009), San Francisco, California, pp. 139-144, August 2009.
  201. J. Cong and G. Luo. A 3D Physical Design Flow Based on OpenAccess. International Conference on Communications, Circuits and Systems (ICCCAS) San Jose California, pp. 1103-1107, July 2009. (Invited Paper).
  202. A. Papakonstantinou, K. Gururaj, J. A. Stratton, D. Chen, J. Cong, and W. W. Hwu. FCUDA: Enabling Efficient Compilation of CUDA Kernels onto FPGAs. Symposium on Application Specific Processors, pp 35-42, July 2009. (Best Paper Award). (Induction to FPGA and Reconfigurable Computing Hall of Fame 2022).
  203. J. Cong, M. F. Chang, G. Reinman, and S.-W. Tam. Multiband RF-Interconnect for Reconfigurable Network-on-Chip Communication. System Level Interconnect Prediction (SLIP 2009), San Francisco California, pp. 107-108, July 2009.
  204. A. Papakonstantinou, K. Gururaj, J. Stratton, D. Chen, J. Cong, W. Hwu. High-Performance CUDA Kernel Execution on FPGAs. ACM/SIGARCH 23rd International Conference on Supercomputing, Metro New York City Area, pp. 515-516, June 2009.
  205. J. Cong and K. Minkovich. Logic Synthesis for Better Than Worst-case Designs. Proceedings International Symposium on VLSI Design, Automation and Test, pp. 166-169, April 2009.
  206. J. Cong, K. Gururaj, B. Liu, C. Liu, Z. Zhang, S. Zhou and Y. Zou. Evaluation of Static Analysis Techniques for Fixed-Point Precision Optimization. Proceedings 17th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2009), Napa, California, pp. 231-234, April 2009.
  207. J. Cong and K. Gururaj. Energy Efficient Multiprocessor Task Scheduling under Input-dependent Variation. Proceedings of Design, Automation and Test in Europe, pp. 411-416, April 2009.
  208. J. Cong, K. Gururaj, and G. Han. Synthesis of Reconfigurable High-Performance Multicore Systems. Proceedings of Field Programmable Gate Arrays, Monterey, California, pp. 201-208, February 2009.
  209. J. Cong and G. Luo. A Multilevel Analytical Placement for 3D ICs. Proceedings of the 14th Asia and South Pacific Design Automation Conference (ASP-DAC 2009), Yokohama, Japan, pp. 361-366, January 2009.
  210. J. Cong, P. Gupta and J. Lee. On the Futility of Statistical Power Optimization. Proceedings of the 14th Asia and South Pacific Design Automation Conference (ASP-DAC 2009), Yokohama, Japan, pp. 167-172, January 2009.
  211. M. F. Chang, J. Cong, A. Kaplan, C. Liu, M. Naik, J. Premkumar, G. Reinman, E. Socher, and R. Tam. Power Reduction of CMP Communication Networks via RFInterconnects. Proceedings of the 41st Annual International Symposium on Microarchitecture (MICRO), Lake ComoItaly pp. 376-387, November 2008.
  212. J. Cong, K. Gururaj, G. Han, A. Kaplan, M. Naik and G. Reinman. MC-Sim: An efficient simulation tool for MPSoC designs. Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design (ICCAD 2008), San Jose, CA, pp. 364-371, November 2008.
  213. A. Agarwal, J. Cong, and B. Tagiku. Fault Tolerant Placement and Defect Reconfiguration for nano-FPGAs. Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design (ICCAD 2008), San Jose, CA, pp. 714-721, November 2008.
  214. J. Cong, C. Liu, and G. Luo. Quantitative Studies of Impact of 3D IC Design on Repeater Usage. Proceedings of 25th International VLSI/ULSI Multilevel Interconnection Conference (VMIC), Fremont, CA, pp. 344-348, October 2008.(Invited Paper).
  215. J. Cong, J. Lee, and L. Vandenberghe. Robust Gate Sizing via Mean Excess Delay Minimization. Proceedings of the 2008 ACM International Symposium on Physical Design, Portland, Oregon, pp. 10-14, April 2008.
  216. M.-C. F. Chang, E. Socher, S.-W. Tam, J. Cong, and G. Reinman. RF Interconnects for Communications On-chip. Proceedings of the 2008 ACM International Symposium on Physical Design, Portland, Oregon, pp. 78-83, April 2008. (Invited Paper).
  217. J. Cong and G. Luo. Highly Efficient Gradient Computation for Density-Constrained Analytical Placement Methods. Proceedings of the 2008 ACM International Symposium on Physical Design, Portland, Oregon, pp. 39-46, April 2008.
  218. J. Cong and J. Xu. Simultaneous FU and Register Binding Based on Network Flow Method. Design, Automation and Test in Europe (DATE 2008), Munich, Germany, pp.1057-1062, March 2008.
  219. J. Cong and Y. Zou. Lithographic Aerial Image Simulation with FPGA-Based Hardware Acceleration. Proc. 16th ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA 2008), Monterey, CA, pp. 20-29, February 2008.
  220. J. Cong and K. Minkovich. Mapping for Better Than Worst-Case Delays In LUT-Based FPGA Designs. Proc. 16th ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA 2008), Monterey, CA, pp. 56-64, February 2008.
  221. J. Cong and W. Jiang. Pattern-based Behavior Synthesis for FPGA Resource Reduction. Proc. 16th ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA 2008), Monterey, CA, pp. 107-116, February 2008.
  222. M. Chang, J. Cong, A. Kaplan, M. Naik, G. Reinman, E. Socher and S.W. Tam. CMP Network-on-Chip Overlaid With Multi-Band RF-Interconnect. The 14th International Symposium on High-Performance Computer Architecture, Salt Lake City, UT, pp. 191-202, February 2008. (Best Paper Award).
  223. X. Li, Y. Ma, X. Hong, S. Dong, and J. Cong. LP Based White Space Redistribution for Thermal Via Planning and Performance Optimization in 3D ICs. Proc. Asia and South Pacific Design Automation Conference (ASP-DAC 2008), pp. 209-212, January 2008.
  224. C.T. Hsieh, J. Cong, Z. Zhang and S.C. Chang. Behavioral Synthesis with Activating Unused Flip-Flops for Reducing Glitch Power in FPGA. Proc. Asia and South Pacific Design Automation Conference (ASP-DAC 2008), pp. 10-15, January 2008.
  225. W. Jiang, Z. Zhang, M. Potkonjak and J. Cong. Scheduling with Integer Time Budgeting for Low-Power Optimization. Proc. Asia and South Pacific Design Automation Conference (ASP-DAC 2008), pp. 22-27, January 2008.
  226. Y. Liu, Y. Ma, E. Kursun, G. Reinman and J. Cong. Fine Grain 3D Integration for Microarchitecture Design Through Cube Packing Exploration. Proc. IEEE International Conference on Computer Designs, Lake Tahoe, CA, pp. 259-266, October 2007.
  227. J. Cong, Y. Ma, Y. Liu, E. Kursun, and G. Reinman. 3D Architecture Modeling and Exploration. Proceedings of 24th International VLSI/ULSI Multilevel Interconnection Conference (VMIC), Fremont, CA, pages 231-238, September 2007.
  228. J. Cong, and K. Minkovich. Improved SAT-Based Boolean Matching Using Implicants for LUT-Based FPGAs. Proceedings of the 15th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, CA, pp. 139-147, February 2007.
  229. J. Cong, G. Han, and W. Jiang. Synthesis of an Application-Specific Soft Multiprocessor System. Proceedings of the 15th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, CA, pp. 99-107, February 2007.
  230. Y. Ma, Z. Li, J. Cong, X. Hong, G. Reinman, S. Dong, and Q. Zhou. Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning. Proceedings of the 12th Asia and South Pacific Design Automation Conference (ASP-DAC 2007), Yokohama, Japan, pp. 920-925, January 2007.
  231. J. Cong, G. Luo, J. Wei, and Y. Zhang. Thermal-Aware 3D IC Placement via Transformation. Proceedings of the 12th Asia and South Pacific Design Automation Conference (ASP-DAC 2007), Yokohama, Japan, pp. 780-785, January 2007. (The ASP-DAC 2017 Ten-Year Retrospective Most Influential Paper Award).
  232. D. Chen, J. Cong, Y. Fan, and Z. Zhang. High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs. Proceedings of the 12th Asia and South Pacific Design Automation Conference (ASP-DAC 2007), Yokohama, Japan, pp. 529-534, January 2007.
  233. J. Cong, Y. Fan, and W. Jiang. Platform-Based Resource Binding Using a Distributed Register-File Microarchitecture. Proc. ACM/IEEE International Conference on Computer Aided Design, San Jose, California, pp. 709-715, November 2006.
  234. J. Cong and Y. Zhang. Thermal-Aware Physical Design Flow for 3-D ICs. Proceedings of the 23rd International VLSI Multilevel Interconnection Conference (VMIC), pp. 73-80, Fremont, CA, September, 2006.
  235. J. Cong, Y. Fan, G. Han, W. Jiang, and Z. Zhang. Platform-Based Behavior-Level and System-Level Synthesis. Proceedings of IEEE International SOC Conference, pp. 199-202, Austin, Texas, Sept. 2006. (Invited Paper).
  236. D. Chen, J. Cong, Y. Fan and J. Xu. Optimality Study of Resource Binding with Multi-Vdds. Proceedings of the 2006 Design Automation Conference, San Francisco, CA, pp. 580-585, July 2006.
  237. J.Y. Lin, D. Chen and J. Cong. Optimal Simultaneous Mapping and Clustering for FPGA Delay Optimization. Proceedings of the 2006 Design Automation Conference, San Francisco, CA, pp. 472-477, July 2006.
  238. J. Cong, Y. Fan, G. Han, W. Jiang and Z. Zhang. Behavior and Communication Co-Optimization for Systems with Sequential Communication Media. Proceedings of the 2006 Design Automation Conference, San Francisco, CA, pp. 675-678, July 2006.
  239. J. Cong and Z. Zhang. An Efficient and Versatile Scheduling Algorithm Based On SDC Formulation. Proceedings of the 2006 Design Automation Conference, San Francisco, CA, pp. 433-438, July 2006. (Induction to FPGA and Reconfigurable Computing Hall of Fame 2022).
  240. J. Cong, T. Chan, J. Shinnerl, K. Sze and M. Xie. mPL6: Enhanced Multilevel Mixed-size Placement. Proceedings of the ACM International Symposium on Physical Design (ISPD 2006), San Jose, CA, pp. 212-214, April 2006.
  241. J. Cong and K. Minkovich. Optimality Study of Logic Synthesis for LUT-Based FPGAs. Proceedings of the 14th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, CA, pp. 33-40, January 2006.
  242. J. Cong, A. Jagannathan, Y. Ma, G. Reinman and J. Wei. An Automated Design Flow for 3D Microarchitecture Evaluation. Proceedings of the 11th Asia and South Pacific Design Automation Conference (ASP-DAC 2006), Yokohama, Japan, pp.384-389, January 2006.
  243. J. Cong and Min Xie. A Robust Detailed Placement for Mixed-Size IC Designs. Proceedings of the 11th Asia and South Pacific Design Automation Conference (ASP-DAC 2006), Yokohama, Japan, pp. 188-194, January 2006.
  244. J. Cong, M. Romesis and J. Shinnerl. Robust Mixed-Size Placement Under Tight White-Space Constraints. Proceedings of the 2005 IEEE/ACM International Conference on Computer Aided Design, San Jose, CA, pp. 165-172, November 2005.
  245. J. Cong and Y. Zhang. Thermal Via Planning for 3-D ICs. Proceedings of the 2005 IEEE/ACM International Conference on Computer Aided Design, San Jose, CA, pp. 745-752, November 2005.
  246. J. Cong, G. Han and Z. Zhang. Architecture and Compilation for Data Bandwidth Improvement in Configurable Embedded Processors. Proceedings of the 2005 IEEE/ACM International Conference on Computer Aided Design, San Jose, CA, pp. 263-270, November 2005.
  247. J. Cong, A. Jagannathan, G. Reinman and Y. Tamir. Understanding the Energy Efficiency of SMT and CMP with Multiclustering. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, San Diego, CA, pp. 48-53, August 2005.
  248. J. Xu, J. Cong and X. Cheng. Lower-Bound Estimation for Multi-Bitwidth Scheduling. Proceedings of the International Symposium on Circuits and Systems, Kobe, Japan, pp. 856-861, May 2005.
  249. T. Chan, J. Cong, and K. Sze. Multilevel Generalized Force-directed Method for Circuit Placement. Proceedings of the International Symposium on Physical Design, San Francisco, CA, pp. 185-192, April 2005.(Best Paper Award).
  250. J. Cong, Y. Fan, G. Han, A. Jagannathan, G. Reinman and Z. Zhang. Instruction Set Extension with Shadow Registers for Configurable Processors. Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, CA, pp. 99-106, February 2005.
  251. G. Chen and J. Cong. Simultaneous Timing-Driven Placement and Duplication. Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, CA, pp. 51-59, February 2005.
  252. J. Cong, and Y. Zhang. Thermal-Driven Multilevel Routing for 3-D ICs. Proceedings of the Asia South Pacific Design Automation Conference, pp.121-126, January 2005. (The ASPDAC 2015 Ten Year Retrospective Most Influential Paper Award).
  253. J. Cong, Y. Fan, G. Han, Y. Lin, J. Xu, Z. Zhang, and X. Cheng. Bitwidth-Aware Scheduling and Binding in High-Level Synthesis. Proceedings of the Asia South Pacific Design Automation Conference, pp. 856-861, January 2005.
  254. D. Chen, J. Cong, and J. Xu. Optimal Module and Voltage Assignment for Low-Power. Proceedings of the Asia South Pacific Design Automation Conference, pp. 51-59, January 2005.
  255. J. Cong, M. Romesis, and J. Shinnerl. Fast Floorplanning by Look-Ahead Enabled Recursive Bipartitioning. Proceedings of the Asia South Pacific Design Automation Conference, pp. 1119-1122, January 2005.
  256. A. Jagannathan, H. Yang, K. Konigsfeld, D. Milliron, M. Mohan, M. Romesis, G. Reinman, and J. Cong. Micro-Architecture Evaluation with Floorplanning and Interconnect Pipelining. Proceedings of the Asia South Pacific Design Automation Conference, pp. 8-15, January 2005. (invited paper).
  257. J. Cong, J. Wei, and Y. Zhang. A Thermal-Driven Floorplanning Algorithm for 3D ICs. Proceedings of the International Conference on Computer-Aided Design, pp. 306-313, November 2004. (The ICCAD 2014 Ten Year Retrospective Most Influential Paper Award).
  258. C. Li, M. Xie, C.K. Koh, J. Cong, and P. Madden. Routability-Driven Placement and White Space Allocation. Proceedings of the International Conference on Computer-Aided Design, pp. 394-401, November 2004.
  259. D. Chen, and J. Cong. DAOmap : A Depth-Optimal Area Optimization Mapping Algorithm for FPGA Designs. Proceedings of the International Conference on Computer-Aided Design, pp. 752-759, November 2004.
  260. J. Cong, A. Jagannathan, G. Reinman and Y. Tamir. A Communication-Centric Approach to Instruction Steering For Future Clustered Processors. Proceedings of the First Watson Conference on Interaction between Architecture, Circuits, and Compilers, Yorktown Heights, pp.144-153, NY, October, 2004 (PAC-2).
  261. G. Chen and J. Cong. Simultaneous Timing Driven Clustering and Placement for FPGAs. Proc. International Conference on Field Programmable Logic and its Applications, pp. 158-167, August 2004.
  262. D. Chen, and J. Cong. Delay Optimal Low-Power Circuit Clustering for FPGAs with Dual Supply Voltages. International Symposium on Low Power Electronics and Design, August 2004, pp. 70 - 73.
  263. J. Cong, Y. Fan, and Z. Zhang. Architecture-Level Synthesis for Automatic Interconnect Pipelining. Proceedings of the Design Automation Conference, pp. 602 - 607, June 2004.
  264. J. Cong, G. Nataneli, M. Romesis, and J. Shinnerl. An Area-Optimality Study of Floorplanning. Proceedings of the International Symposium on Physical Design, pp. 78 - 83, April 2004.
  265. D. Chen, J. Cong, F. Li, and L. He. Low-Power Technology Mapping for FPGA Architectures with Dual Supply Voltages. Proceedings of the ACM International Symposium on Field-Programmable Gate Arrays, pp. 109 - 117, February 2004.
  266. J. Cong, Y. Fan, G. Han, and Z. Zhang,. Application-Specific Instruction Generation for Configurable Processor Architectures. Proceedings of the ACM International Symposium on Field-Programmable Gate Arrays, pp. 183 - 189, February 2004.
  267. F. Li, Y. Lin, L. He, and J.Cong. Low-power FPGA using Pre-Defined Dual-Vdd/Dual-Vt Fabrics. Proceedings of the ACM International Symposium on Field-Programmable Gate Arrays, pp. 42 - 50 , February 2004.
  268. D. Chen, and J. Cong. Register Binding and Port Assignment for Multiplexer Optimization. Proceedings of the Asia Pacific Design Automation Conference, pp. 68 - 73, January 2004.
  269. J. Cong, T. Kong, J. Shinnerl, M. Xie and X. Yuan. Large-Scale Circuit Placement. Proceedings of International Conference on Computer Aided Design,, pp. 883-890, November 2003.
  270. T. F. Chan, J. Cong, J. Shinnerl and K. Sze. An Enhanced Multilevel Algorithm for Circuit Placement. Proceedings of International Conference on Computer Aided Design, pp. 299-306, November 2003.
  271. Z. Zhang, Y. Fan, M. Potkonjak and J. Cong. Gradual Relaxation Technique with Application to Behavioral Synthesis. Proceedings of International Conference on Computer Aided Design,, pp. 529-535, November 2003.
  272. J. Cong, Y. Fan, G. Han X. Yang and Z. Zhang. Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication. Proceedings of International Conference on Computer Aided Design,, pp. 536-543, November 2003.
  273. J. Cong, M. Romesis, and M. Xie. Optimality and Stability Study of Timing-driven Placement Algorithms. Proceedings of International Conference on Computer Aided Design,, pp. 472-478, November 2003.
  274. D. Chen, J. Cong, and Y. Fan. Low-Power High-Level Synthesis for FPGA Architectures. 2003 International Symposium on Low Power Electronics and Design, Seoul, Korea, pp. 134 - 139, Aug. 2003.
  275. J. Cong, A. Jagannathan, G. Reinman and M. Romesis. Microarchitecture Evaluation with Physical Planning. ACM/SIGDA Proceedings of the 40th Design Automation Conference, Anaheim, California, pp. 32 - 35, June 2003.
  276. J. Cong, and X. Yuan. Multilevel Global Placement with Retiming. ACM/SIGDA Proceedings of the 40th Design Automation Conference, Anaheim, California, pp. 208 - 213, June 2003.
  277. J. Cong, Y. Fan, X. Yang and Z. Zhang. Architecture and Synthesis for Multi-Cycle Communication. ACM/SIGDA Proceedings of 2003 International Symposium on Physical Design, Monterey, California, pp. 190-196, April 2003.(Invited paper).
  278. J. Cong, M. Romesis and M. Xie. Optimality, Scalability and Stability Study of Partitioning and Placement Algorithms. Proceedings of the International Symposium on Physical Design, Monterey, California, pp. 88 - 94, April 2003.
  279. J. Y. Lin, A. Jagannathan and J. Cong. Placement-Driven Technology Mapping For LUT-Based FPGAs. ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, California, pp. 121 - 126, February 2003.
  280. F. Li, D. Chen, L. He, and J. Cong. Architecture Evaluation for Power-Efficient FPGAs. ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, California, pp. 175 - 184, February 2003.
  281. C.-C. Chang, J. Cong and X. Yuan. Multi-level Placement for Large-Scale Mixed-Size IC Designs. Proc. Asia South Pacific Design Automation Conference, pp. 325-330, January 2003.
  282. C.-C. Chang, J. Cong and M. Xie. Optimality and Scalability Study of Existing Placement Algorithms. Asia South Pacific Design Automation Conference, Kitakyushu, Japan, pp. 621-627, January 2003.
  283. J. Cong, J. Y. Lin and W. Long. A New Enhanced SPFD Rewiring Algorithm. Proc. IEEE International Conference on Computer Aided Design, San Jose, California, pp. 672-678, November 2002 .
  284. J. Cong, M. Xie and Y. Zhang. An Enhanced Multilevel Routing System. Proc. IEEE International Conference on Computer Aided Design, San Jose, California, pp. 51-58, November 2002.
  285. J. Cong, J. Y. Lin and W. Long. Enhanced SPFD Rewiring on Improving Rewiring Ability. IWLS, pp. 91 - 96, June 2002 .
  286. J. Cong. Timing Closure Based on Physical Hierarchy. Proc. International Symposium on Physical Design, San Diego, California, pp. 170-174, April 2002. (Invited paper).
  287. J. Cong, and C. Wu. Global Clustering-Based Performance-Driven Circuit Partitioning. Proc. International Symposium on Physical Design, San Diego, California, pp. 149-154, April 2002.
  288. C-C. Chang, J. Cong, Z. Pan and X. Yuan. Physical Hierarchy Generation with Routing Congestion Control. Proc. International Symposium on Physical Design, San Diego, California, pp. 36-41, April 2002.
  289. J. Cong, Y. Lin and W. Long. SPFD-Based Global Rewiring. Proc. ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, California, pp. 77-84, February 2002.
  290. J. Cong, J. Fang and Y. Zhang. Multilevel Approach to Full-Chip Gridless Routing. Proc. IEEE International Conference on Computer Aided Design, San Jose, California, pp. 396-403, November 2001.
  291. C. Chang, J. Cong, T. Uchinko and X. Yuan. Power Model for Interconnect Planning. Procedings of the Workshop on Synthesis And System Integration of Mixed Technologies, pp. 234 - 241, October 2001.
  292. J. Cong. An Interconnect-Centric Design Flow for Nanometer Technologies. Proceedings of the Workshop on Synthesis And System Integration of Mixed Technologies, pp. 199 - 205, October 2001. (Invited paper).
  293. J. Cong and W. Long. SPFD-Based Global Rewiring. 10th International Workshop on Logic & Synthesis, pp. 150-155, June 2001.
  294. J. Cong and T. Uchinko. An Interconnect Energy Model Considering Coupling Effects. Proceedings of the 38th Design Automation Conference, pp. 555-558, June 2001.
  295. J. Cong and M. Romesis. Performance-Driven Multi-Level Clustering with Application to Hierarchical FPGA Mapping. Proceedings of the Design Automation Conference, pp. 389-394, Las Vegas, Nevada, June 2001.
  296. J. Cong, D. Z. Pan and P. V. Srinivas. Improved Crosstalk Modeling for Noise Constrained Interconnect Optimization. Proc. Asian and South Pacific Design Automation Conference (ASPDAC), pp. 373-378, Pacifico Yokohama, Japan, 2001.
  297. G. Chen and J. Cong. Simultaneous Logic Decomposition with Technology Mapping in FPGA Designs. Proc. ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, California, pp. 48-55, February 2001.
  298. D. Chen, J. Cong, M. Ercegovac and Z. Huang. Performance-Driven Mapping for CPLD Architecture. Proc. ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, California, pp. 39-47, February 2001.
  299. J. Cong, D. Z. Pan and P. V. Srinivas. Improved Crosstalk Modeling for Noise Constrained interconnect Optimization. ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, pp. 14-20, Austin, December 2000.
  300. O. Goundert, J. Cong, S. Malik and M. Sarrafzadeh. Incremental CAD. Proc. IEEE International Conference on Computer Aided Design, San Jose, California, pp. 236-243, November 2000.
  301. T. Chan, J. Cong, T. Kong and J. Shinnerl. Multilevel Optimization for Large-scale Circuit Placement. Proc. IEEE International Conference on Computer Aided Design, San Jose, California, pp. 171-176, November 2000.
  302. J. Cong and S. K. Lim. Physical Planning with Retiming. Proc. IEEE International Conference on Computer Aided Design, San Jose, California, pp. 2-7, November 2000.
  303. J. Cong, H. Huang, Yean-Yow Hwang, C. Wu and S. Xu. fpgaEva: A Logic-Level Architecture Evaluator for SRAM-Based FPGAs. Proc. of 16th IFIP World Computer Congress - ICDA'2000: Chip Design Automation, Beijing, P.R. China, pp. 179-184, August 2000.
  304. J. Cong, S. K. Lim and Chang Wu. Performance Driven Multi-level and Multiway Partitioning With Retiming. Proc. ACM/IEEE 37th Design Automation Conference, , Los Angeles, California, pp. 274-279, June 2000.
  305. J. Cong and X. Yuan. Routing Tree Construction Under Fixed Buffer Locations. Proc. ACM/IEEE 37th Design Automation Conference, Los Angeles, California, pp. 379-384, June 2000.
  306. J. Cong and H. Huang. Depth Optimal Incremental Mapping for Field Programmable Gate Arrays. Proc. ACM/IEEE 37th Design Automation Conference, , Los Angeles, California, pp. 290-293, June 2000.
  307. J. Cong and M. Sarrafzadeh. Incremental Physical Design. Proc. International Symposium on Physical Design, , San Diego, California, pp. 84-92, April 2000.
  308. C.-C. Chang and Jason Cong. Pseudo Pin Assignment with Crosstalk Noise Control. Proc. International Symposium on Physical Design, , San Diego, California, pp. 41-47, April 2000.
  309. J. Cong, J. Fang and K.-Y. Khoo. DUNE: A Multi-Layer Gridless Routing System with Wire Planning. Proc. International Symposium on Physical Design, , San Diego, California, pp. 12-18, April 2000.
  310. J. Cong and K. Yan. Synthesis for FPGAs with Embedded Memory Blocks. Proc. ACM/SIGDA International Symposium on Field Programmable Gate Arrays, San Jose, California, Feb. 2000, pp. 75-82, February 2000.
  311. J. Cong, H. Huang and X. Yuan. Technology Mapping for k/m-macrocell Based FPGAs. Proc. ACM/SIGDA International Symposium on Field Programmable Gate Arrays, San Jose, California, pp. 51-59, February 2000.
  312. M. Wang, S. K. Lim, J. Cong and M. Sarrafzadeh. Multi-way Partitioning Using Bi-partition Heuristics. Asia South Pacific Design Automation Conference, Yokohama Japan, pp. 667-672, January 2000.
  313. J. Cong and S. K. Lim. Performance Driven Multiway Partitioning. Asia South Pacific Design Automation Conference, Yokohama Japan, pp. 441-446, January 2000.
  314. J. Cong and S. K. Lim. Edge Separability based Circuit Clustering With Application to Circuit Partitioning. Asia South Pacific Design Automation Conference, Yokohama Japan, pp. 429-434, January 2000.
  315. J. Cong and Songjie Xu. Synthesis Challenges for Next-Generation High-Performance and High-Density PLDs. Asia and South Pacific Design Automation Conference, Yokohama, Japan, pp. 157-162, January 2000. (Invited Talk).
  316. J. Cong, T. Kong and D.Z. Pan. Buffer Block Planning for Interconnect-Driven Floorplanning. Proc. ACM/IEEE International Conference on Computer Aided Design, San Jose, California, pp. 358-363, November 1999.
  317. J. Cong, J. Fang and K.Y. Khoo. An Implicit Connection Graph Maze Routing Algorithm for ECO Routing. Proc. ACM/IEEE International Conference on Computer Aided Design, San Jose, California, pp. 163-167, November 1999.
  318. J. Cong and D.Z. Pan. Interconnect Estimation and Planning for Deep Submicron Designs. Proc. 36th ACM/IEEE Design Automation Conf., New Orleans, Louisiana, pp. 507-510, June 1999.
  319. J. Cong, H. Li and C. Wu. Simultaneous Circuit Partitioning/Clustering with Retiming for Performance Optimization. Proc. 36th ACM/IEEE Design Automation Conf., New Orleans, Louisiana, pp. 460-465, June 1999.
  320. J. Cong, Y.-Y. Hwang and Songjie Xu. Technology Mapping for FPGAs with Nonuniform Pin Delays and Fast Interconnections. Proc. 36th ACM/IEEE Design Automation Conf., New Orleans, Louisiana, pp. 373-378, June 1999.
  321. J. Cong. An Interconnect-Centric Design Flow for Nanometer Technologies. Proc. of Int'l Symp. on VLSI Technology, Systems, and Applications, Taipei, Taiwan, pp. 54-57, June 1999. (Invited Talk) .
  322. J. Cong, J. Fang and K.-Y. Khoo. Via Design Rule Consideration in Multi-Layer Maze Routing Algorithms. Proc. Intl Symposium on Physical Design, Monterey, California, pp. 214-220, April 1999.
  323. C.-C. Chang and J. Cong. Crosstalk Noise Control in Gridless General-Area Routing. ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), Monterey, California, pp. 117-122, March 8-9, 1999.
  324. J. Cong and David Z. Pan. Interconnect Delay and Area Estimation for Multiple-Pin Nets. ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), Monterey, California, pp. 179-184, March 8-9, 1999.
  325. J. Cong, C. Wu and E. Ding. Cut Ranking and Pruning: Enabling A General And Efficient FPGA Mapping Solution. Proc. ACM Intl. Symp. on FPGA, Monterey, California, pp. 29-35, February 1999. (Selected for FPGA20: the most significant contributions in the FPGA Symposium from 1992 – 2011)..
  326. J. Cong and D. Z. Pan. Interconnect Delay Estimation Models for Synthesis and Design Planning. Proc. of ASP-DAC'99 Hong Kong, China, pp. 97-100, January 1999.
  327. J. Cong, T. Kong, D. Xu, F. Liang, J. S. Liu and W. H. Wong. Relaxed Simulated Tempering for VLSI Floorplan Designs. Proc. of ASP-DAC'99 Hong Kong, China, pp. 13-16, January 1999.
  328. J. Cong and S. K. Lim. Multiway Partitioning with Pairwise Movement. Proc. ACM/IEEE International Conference on Computer Aided Design, San Jose, California, pp. 512-516, November 1998.
  329. D. Kirovski, Y.-Y. Hwang, M. Potkonjak and J. Cong. Intellectual Property Protection by Watermarking Combinational Logic Synthesis Solutions. Proc. ACM/IEEE International Conference on Computer Aided Design, San Jose, California, pp. 194-198, November 1998.
  330. J. Cong and S. Xu. Delay-Oriented Technology Mapping for Heterogeneous FPGAs with Bounded Resources. Proc. ACM/IEEE International Conference on Computer Aided Design, San Jose, California, pp. 40-45, November 1998.
  331. J. Cong and S. Xu. Delay-Optimal Technology Mapping for FPGAs with Heterogeneous LUTs. Proc. of 35th Design Automation Conf., San Francisco, California, pp. 704-707, June 1998.
  332. J. Cong and Z. Pan. Interconnect Performance Estimation Models for Synthesis and Design Planning. ACM/IEEE Int'l Workshop on Logic Synthesis, pp. 427-433, June 1998.
  333. J. Cong and P. Madden. Performance Driven Multi-Layer General Area Routing for PCB/MCM Designs. Proc. of 35th Design Automation Conf., San Francisco, California, pp. 356-361, June 1998.
  334. J. Cong and C. Wu . Optimal FPGA Mapping and Retiming with Efficient Initial State Computation. Proc. of 35th Design Automation Conf., San Francisco, California, pp. 330-335, June 1998.
  335. J. Cong. Challenges and Opportunities for Design Innovations in Nanometer Technologies. Invited Semiconductor Research Corporation Design Sciences Concept Paper, pp. 1 - 15, January 1998. (Also appeared in the International Symposium on Computing and Microelectronics Technologies, May 1998).
  336. Cong, J. and L. He. An Efficient Technique for Device and Interconnect Optimization in Deep Submicron Designs. ACM Int'l Symposium on Physical Design, pp 45-51, April, 1998.
  337. J. Cong and S. Xu . Technology Mapping for FPGAs with Embedded Memory Blocks. Proc. ACM International Symposium on FPGA, Monterey, California, pp. 179-188, February 1998.
  338. J. Cong and Y. Hwang. Boolean Matching for Complex PLBs in LUT based FPGAs with Application to Architecture Evaluation. Proc. ACM International Symposium on FPGA, Monterey, California, pp. 27-34, February 1998.
  339. J. Cong and C. K. Koh. Interconnect Layout Optimization Under Higher-Order RLC Model. Proc. IEEE Int'l Conf. on Computer-Aided Design, San Jose, California, pp. 713-720, November 1997.
  340. J. Cong, L. He, C. K. Koh and Z. Pan. Global Interconnect Sizing and Spacing with Consideration of Coupling Capacitance. Proc. IEEE Int'l Conf. on Computer-Aided Design, San Jose, California, pp. 628-633, November 1997.
  341. J. Cong, H. P. Li, S. K. Lim, T. Shibuya and D. Xu. Large Scale Circuit Partitioning with Loose/Stable Net Removal and Signal Flow Based Clustering. Proc. IEEE Int'l Conf. on Computer-Aided Design, San Jose, California, pp. 441-446, November 1997.
  342. J. Cong, L. He, K. Y. Khoo, C. K. Koh and Z. Pan. Interconnect Design for Deep Submicron ICs. Proc. IEEE Int'l Conf. on Computer-Aided Design, San Jose, California, pp. 478-485, November 1997. (Invited Embedded Tutorial) .
  343. J. Cong and C. Wu. FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential Circuits. Proc. 34th ACM/IEEE Design Automation Conf., Anaheim, California, pp. 644-649, June 1997.
  344. J. Cong, L. He, A. B. Kahng, D. Noice, N. Shirali and S. H.-C. Yen. Analysis and Justification of a Simple, Practical 2 1/2-D Capacitance Extraction Methodology. Proc. 34th ACM/IEEE Design Automation Conf., Anaheim, California, pp. 627-632, June 1997.
  345. C.- C. Chang. and J. Cong. An Efficient Approach to Multi-layer Layer Assignment with Application to Via Minimization. Proc. 34th ACM/IEEE Design Automation Conf., Anaheim, California, pp. 600-603, June 1997.
  346. J. Cong and K.-S. Leung. Fast Optimal Algorithms for the Minimum Rectilinear Steiner Arborescence Problem. Proc. Intl Symposium on Circuits and Systems, pp. 1568-1571, May 1997.
  347. J. Cong, A. B. Kahng and K.-S. Leung. Efficient Heuristics for the Minimum Shortest Path Steiner Arborescence Problem with Applications to VLSI Physical Design. Proc. Intl Symposium on Physical Design, Napa, California, pp. 88-95, April 1997.
  348. J. Cong and Patrick H. Madden. Performance Driven Global Routing for Standard Cell Design. Proc. Intl Symposium on Physical Design, Napa, California, pp 73-80, April 1997.
  349. J. Cong and Y. Hwang. Partially-Dependent Functional Decomposition with Applications in FPGA Synthesis and Mapping. Proc. ACM/SIGDA Int'l Symp. on Field-Programmable Gate-Arrays, Monterey, California, pp. 35-42, February 1997.
  350. J. Cong. Modeling and Layout Optimization of VLSI Devices and Interconnects In Deep Submicron Design. Proc. Asia and South Pacific Design Automation Conf., Chiba, Japan, pp. 121-126, January 1997.
  351. J. Cong and L. He. An Efficient Approach to Simultaneous Transistor and Interconnect Sizing. Proc. IEEE Int'l Conf. on Computer-Aided Design, San Jose, California, pp. 181-186, November 1996.
  352. T. Okamoto and J. Cong. Buffered Steiner Tree Construction with Wire Sizing for Interconnect Layout Optimization. Proc. IEEE Int'l Conf. on Computer-Aided Design, San Jose, California, pp. 44-49, November 1996.
  353. J. Cong and C. Wu. An Improved Algorithm for Performance-Optimal Technology Mapping with Retiming in LUT-Based FPGA Design. Proc. IEEE Int'l Conf. on Computer Design, Austin, Texas, pp. 572-578, October 1996.
  354. J. Cong, C. K. Koh and K. S. Leung. Simultaneous Buffer and Wire Sizing for Performance and Power Optimization. Proc. IEEE Int'l Symp. on Low Power Electronics and Design., Monterey, California, pp 271-276, August 1996.
  355. J. Cong and Y. Y. Hwang. Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-based FPGA Design. Proc. 33rd ACM/IEEE Design Automation Conf., pp. 726-729, June 1996.
  356. J. Cong and L. He. Simultaneous Transistor and Interconnect Sizing Using General Dominance. Proc. 5th ACM/SIGDA Physical Design Workshop, Reston Virginia, pp. 34-39, April 1996.
  357. T. Okamoto and J. Cong. Interconnect Layout Optimization by Simultaneous Steiner Tree Construction and Buffer Insertion. Proc. 5th ACM/SIGDA Physical Design Workshop, Reston, Virginia, pp. 1-6, April 1996.
  358. J. Cong, J. Peck and Y. Ding. RASP: A General Logic Synthesis System for SRAM-based FPGAs. Proc. ACM/SIGDA Int'l Symp. on Field-Programmable Gate-Arrays, Monterey, California, pp. 137 - 143, February 1996.
  359. L. Kleinrock, M. Gerla, N. Bambos, J. Cong, E. Gafni, L. Bergman, J. Bannister, S. Monacos, T. Bujewski, P. C. Hu, B. Kannan, B. Kwan, E. Leonardi, J. Peck, P. Palnati, and S. Walton. The Supercomputer Supernet(SSN): A High-Speed Electro-Optic Campus and Metropolitan Network. Proc. SPIE, San Jose, California, vol. 2692, pp. 22-33, January 1996.
  360. J. Cong and Lei He. Optimal Wiresizing for Interconnects with Multiple Sources. Proc. ACM/IEEE Int'l Conf. on Computer-Aided Design, Santa Clara, California, pp. 568-574, November 1995. (Full version is available as UCLA Tech. Report 95-00031.).
  361. J. Cong, A. B. Kahng, C. K. Koh and C. W. Tsao. Bounded-Skew Clock and Steiner Routing. Proc. ACM/IEEE Int'l Conf. on Computer-Aided Design, Santa Clara, California, pp. 66-71, November 1995.
  362. J. Cong and D. Xu. Exploiting Signal Flow and Logic Dependency in Standard Cell Placement. Proc. Asia and South Pacific Design Automation Conf., Chiba, Japan, pp. 399-404, August 1995.
  363. J. Cong and C. K. Koh. Minimum-Cost Bounded-Skew Clock Routing. Proc. Int'l Symp. on Circuits and Systems, Seattle, Washington, pp. 215-218, May 1995.
  364. J. Cong and P. Madden. Performance Driven Routing with Multiple Sources. Proc. Int'l Symp. on Circuits and Systems, Seattle, Washington, pp. 203-206, May 1995.
  365. J. Cong and Y. Ding. On Nominal Delay Minimization in LUT-Based FPGA Technology Mapping. Proc. ACM/SIGDA Int'l Symp. on Field-Programmable Gate-Arrays, Monterey, California, pp. 82-88, February 1995.
  366. J. Cong and Y. Hwang. Simultaneous Depth and Area Minimization in LUT-Based FPGA Mapping. Proc. ACM/SIGDA Int'l Symp. on Field-Programmable Gate-Arrays, Monterey, California, pp. 68-74, February 1995. (Selected for FPGA20: the most significant contributions in the FPGA Symposium from 1992 – 2011).
  367. R. Bagrodia, Z. Li, V. Jha, Y. Chen and J. Cong. Parallel Logic Level Simulation of VLSI Circuits. Proc. IEEE Winter Simulation Conf., pp. 1354-1361, December 1994.
  368. J. Cong and C. K. Koh. Simultaneous Driver and Wire Sizing for Performance and Power Optimization. Proc. Int'l Conf. on Computer-Aided Design, pp. 206-212, November 1994.
  369. J. Cong, W. Labio and N. Shivakumar. Multi-Way VLSI Circuit Partitioning Based on Dual Net Representations. Proc. Int'l Conf. on Computer-Aided Design, pp. 56-62, November 1994.
  370. J. Cong, Z. Li and R. Bagrodia. Acyclic Multi-Way Partitioning of Boolean Networks. Proc. 31st IEEE/ACM Design Automation Conf., pp. 670-675, June 1994.
  371. J. Cong, C. K. Koh. Simultaneous Driver and Wire Sizing for Performance and Power Optimization. Proc. Int'l Workshop on Low Power Design, pp. 81-86, April 1994.
  372. J. Cong and Y. Ding. Beyond The Combinatorial Limit in Depth Minimization For LUT-Based FPGA Designs. Proc. Int'l Conf. on Computer-Aided Design, pp. 634-639, November 1993.
  373. J. Cong and K. S. Leung. Optimal Wiresizing Under the Distributed Elmore Delay Model. Proc. Int'l Conf. on Computer-Aided Design, pp. 110-114, November 1993.
  374. T. Gao, K. C. Chen, J. Cong, Y. Ding and C. L. Liu. Placement and Placement Driven Technology Mapping for FPGA Synthesis. Proc. IEEE ASIC Conf., pp. 91-94, September 1993.
  375. J. Cong and Y. Ding. An Optimal Performance-Driven Technology Mapping Algorithm For LUT-Based FPGAs Under Arbitrary Net-Delay Models. Proc. Int'l Conf. on Computer-Aided Design and Computer Graphics, pp. 599-604, August 1993.
  376. J. Cong and M. Smith. A Parallel Bottom-up Clustering Algorithm with Applications to Circuit Partitioning in VLSI Designs. Proc. ACM/IEEE 30th Design Automation Conference, pp. 755-760, June 1993.
  377. J. Cong, K. S. Leung and D. Zhou. Performance-Driven Interconnect Design Based on Distributed RC Delay Model. Proc. ACM/IEEE 30th Design Automation Conference, pp. 606-611, June 1993.
  378. K. Y. Khoo and J. Cong. An Efficient Multilayer MCM Router Based on Four-Via Routing. Proc. ACM/IEEE 30th Design Automation Conference, pp. 590-595, June 1993.
  379. J. Cong and Y. Ding. On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping. Proc. ACM/IEEE 30th Design Automation Conference, pp. 213-218, June 1993.
  380. C. J. Alpert, J. Cong, A. B. Kahng, G. Robins and M. Sarrafzadeh. Minimum Density Interconnection Trees. Proc. IEEE Int'l Symp. on Circuits and Systems, pp. 1865-1868, May 1993.
  381. S. Iman, M. Pedram, C. Fabian and J. Cong. Finding Uni-Directional Cuts Based on Physical Partitioning and Logic Restructuring. 4th ACM/SIGDA Physical Design Workshop, pp. 187-198, April 1993.
  382. D. Zhou, F. Tsui, J. Cong, and D. Gao. A distributed-RCL model for MCM layout. Proc. IEEE Multi-Chip Module Conf., pp. 191-197, March 1993.
  383. K. Y. Khoo and J. Cong. A Fast Four-Via Multilayer MCM Router. Proc. IEEE Multi-Chip Module Conf., pp. 179-184, March 1993.
  384. D. Boese, J. Cong, A. Kahng, K. S. Leung and D. Zhou. On High-Speed VLSI Interconnects: Analysis and Design. Proc. IEEE Asia-Pacific Conference on Circuits and Systems, pp. 35-40, December 1992. (Invited paper) .
  385. J. Cong and Y. Ding. An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs. Proc. IEEE Int'l Conference on Computer-Aided Design, pp. 48-53, November 1992. (Highlighted paper).
  386. J. Cong, Y. Ding, A. Kahng, P. Trajmar and K. C. Chen. An Improved Graph-Based FPGA Technology Mapping Algorithm For Delay Optimization. Proc. IEEE Int'l Conference on Computer Design, pp. 154-158, October 1992.
  387. K. Y. Khoo and J. Cong. A Fast Multilayer General Area Router for MCM Designs. Proc. European Design Automation Conference, pp. 292-297, September 1992.
  388. K. C. Chen and J. Cong. Maximal Reduction of Lookup-Table Based FPGAs. Proc. European Design Automation Conference, pp. 224-229, September 1992.
  389. J. Cong, L. Hagen, and A. Kahng. Net Partitions Yield Better Module Partitions. Proc. ACM/IEEE 29th Design Automation Conference, pp. 47-52, June 1992. (Best Paper Award Candidate).
  390. J. Cong, A. Kahng, G. Robins, M. Sarrafzadeh, and C. K. Wong. Provably Good Algorithms for Performance-Driven Global Routing. Proc. IEEE International Symposium on Circuits and Systems, pp. 2240-2243, May 1992.
  391. J. Cong, A. Kahng, P. Trajmar and K. C. Chen. DAG-Map:Graph Based FPGA Technology Mapping for Delay Optimization. Proc. ACM Int'l Workshop on Field Programmable Gate Arrays, pp. 77-82, February 1992.
  392. J. Cong and K. Khoo. A Provable Near-Optimal Algorithm for the Channel Pin Assignment Problem. Proc. IEEE Int'l Conference on Computer Design, pp. 319-322, October 1991.
  393. J. Cong, A. Kahng and G. Robins. Performance-Driven Global Routing for Cell Based ICs. Proc. IEEE Int'l Conference on Computer Design, pp. 170-173, October 1991.
  394. J. Cong, L. Hagen and A. Kahng. Random Walks for Circuit Clustering. Proc. IEEE 4th Int'l ASIC Conf., pp. 14-2.1 - 14-2.4, September 1991.
  395. J. Cong, A. Kahng and G. Robins. On Clock Routing for General Cell Layouts. Proc. IEEE 4th Int'l ASIC Conf., pp. 14-5.1 - 14-5.4, September 1991.
  396. A. Kahng, J. Cong and G. Robins. High-Performance Clock Routing Based on Recursive Geometric Matching. Proc. ACM/IEEE 28th Design Automation Conf., pp. 322-327, June 1991.
  397. J. Cong, B. Preas and C. L. Liu. General Models and Algorithms for Over-the-Cell Routing in Standard Cell Design. Proc. 27th ACM/IEEE Design Automation Conf., pp. 709-715, June 1990.
  398. J. Cong and C. L. Liu. On the k-Layer Planar Subset and Via Minimization Problems. Proc. of European Design Automation Conf., pp. 459-463, March 1990.
  399. J. Cong. Pin Assignment with Global Routing for General Cell Designs. Proc. Int'l Conf. on Computer-Aided Design, pp. 302-305, November 1989.
  400. S. Dong, J. Cong and C. L. Liu. Constrained Floorplan Design for Flexible Blocks. Proc. Int'l Conf. on Computer-Aided Design, pp. 488-491, November 1989.
  401. N. Hasan, J. Cong and C. L. Liu. An Integer Linear Programming Approach to General Fault Covering Problems. Proc. Int'l Workshop on Defect and Fault Tolerance in VLSI Systems, pp. 146-156, October 1989.
  402. K. S. The, D. F. Wong and J. Cong. VIA Minimization by Layout Modification. Proc. 26th ACM/IEEE Design Automation Conf., pp. 799-802, June 1989.
  403. N. Hasan, J. Cong and C. L. Liu. A New Formulation of Yield Enhancement Problems for Reconfigurable Chips. Proc. Int'l Conf. Computer-Aided Design, pp. 520-523, November 1988.
  404. J. Cong and B. Preas. A New Algorithm for Standard Cell Global Routing. Proc. Int'l Conf. on Computer-Aided Design," pp 176-179, November 1988. (Highlighted paper).
  405. J. Cong and C. L. Liu. Over-the-Cell Channel Routing. Proc. Int'l Conf. Computer-Aided Design," pp. 80-83, November 1988.
  406. N. Hasan, J. Cong and C. L. Liu. A General Model for Fault Covering Problems in Reconfigurable Arrays. Proc. Int'l Workshop on Defect and Fault Tolerance in VLSI Systems, pp. 319-326, 1988.
  407. J. Cong and D. F. Wong. How to Obtain More Compactable Channel Routing Solutions. Proc. 25th IEEE/ACM Design Automation Conf., pp 663-666, June 1988.
  408. J. Cong, D. F. Wong and C. L. Liu. A New Approach to Three- or Four-Layer Channel Routing. Proc. Int'l Conf. Computer-Aided Design, pp. 378-381, November 1987.