VAST lab at UCLA

The VAST lab at UCLA investigates cutting-edge research topics at the intersection of VLSI technologies, design automation,  architecture and compiler optimization at multiple scales, from micro-architecture building blocks,  to heterogeneous compute nodes, and scalable data centers.  Current focuses include architecture and design automation for emerging technologies, customizable domain-specific computing with applications to multiple domains, such as imaging processing, bioinformatics, data mining and machine learning.

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Latest News

Thu, Jul 13, 2023

Congratulations to Atefeh Sohrabizadeh, Cody Hao Yu, Jason Cong from UCLA and Min Gao from Falcon Computing for receiving the 2023 Best Paper Award from the ACM Transactions on Design Automation of Electronic Systems (TODAES) for their paper entitled "AutoDSE: Enabling Software Programmers to...

Mon, Jun 26, 2023

Congratulations to Prof. Jason Cong and VAST Lab alumni, Yiping Fan, Guoling Han, Zhiru Zhang for being the Class of 2023 Inductees to the TCFPGA Hall of Fame for the paper “Application-Specific Instruction Generation for Configurable Processor Architectures” (February 2004).


Fri, May 19, 2023

Congratulations to Prof. Jason Cong for receiving the “Global Industry Leader” Award from ChipEx’2023 on May 8, 2023 in Tel Aviv, Israel, for “groundbreaking research and development which revolutionized electronic design automation and FPGA design methods, for co-founding several chip design...

Latest Publications

Point of View: Micro/Nano Circuits and Systems Design and Design Automation: Challenges and Opportunities
Journal publication
Gert Cauwenberghs, Jason Cong, X. Sharon Hu, Subhasish Mitra, Wolfgang Porod, H.-S. Philip Wong
[PDF]: A Comprehensive Automated Exploration Framework for Systolic Array Designs
Conference publication
Suhail Basalama, Jie Wang, Jason Cong
Scalable Optimal Layout Synthesis for NISQ Quantum Processors
Conference publication
Wan-Hsuan Lin, Jason Kimko, Bochen Tan, Nikolaj Bjørner, Jason Cong
NeSSA: Near-Storage Data Selection for Accelerated Machine Learning Training
Conference publication
Neha Prakriya, Yu Yang, Baharan Mirzasoleiman, Cho-Jui Hsieh, Jason Cong
RapidStream 2.0: Automated Parallel Implementation of Latency Insensitive FPGA Designs Through Partial Reconfiguration
Journal publication
Licheng Guo, Pongstorn Maidee, Yun Zhou, Chris Lavin, Eddie Hung, Wuxi Li, Jason Lau, Weikang Qiao, Yuze Chi, Linghao Song, Yuanlong Xiao, Alireza Kaviani, Zhiru Zhang, Jason Cong
FPGA-Based In-Vivo Calcium Image Decoding for Closed-Loop Feedback Applications
Journal publication
Zhe Chen, Garrett J. Blair, Chengdi Cao, Jim Zhou, Daniel Aharoni, Peyman Golshani, Hugh T. Blair, and Jason Cong
FPGA Acceleration of Probabilistic Sentential Decision Diagrams with High-Level Synthesis
Journal publication
Young-kyu Choi, Carlos Santillana, Yujia Shen, Adnan Darwiche, Jason Cong
FlexCNN: An End-to-End Framework for Composing CNN Accelerators on FPGA
Journal publication
Suhail Basalama, Atefeh Sohrabizadeh, Jie Wang, Licheng Guo, and Jason Cong
Callipepla: Stream Centric Instruction Set and Mixed Precision for Accelerating Conjugate Gradient Solver
Conference publication
Linghao Song, Licheng Guo, Suhail Basalama, Yuze Chi, Robert F. Lucas, and Jason Cong

Our Projects

Domain-specific accelerators (DSAs) have shown to offer significant performance and energy efficiency over general-purpose CPUs to meet the ever increasing performance needs. However, it is well-known that the DSAs in field-programmable gate-arrays (FPGAs) or application specific integrated...



  • Compilation in quantum computing (QC)
  • Optimality study - how far are we from optimal?
  • Optimal quantum layout synthesis
  • Exploring architecture design with layout synthesis
  • Layout synthesis for reconfigruable QC...

Heterogeneous computing with extensive use of accelerators, such as FPGAs and GPUs, has shown great promise to bring in orders of magnitude improvement in computing efficiency for a wide range of applications. The latest advances in industry have led to highly integrated heterogeneous hardware...

Direction 1: Real-Time Neural Signal Processing for Closed-Loop Neurofeedback Applications.

The miniaturized fluorescence microscope (Miniscope) and the tetrodes assembly are emerging techniques in observing the activity of a large population of neuros in vivo. It opens up new research...

In the Big Data era, the volume of data is exploding, putting forward a new challenge to existing computer systems. Traditionally, the computer system is designed to be computing-centric, in which the data from IO devices is transferred and then processed by the CPU. However, this data movement...

In this project, we explore efficient algorithms and architectures for state-of-the-art deep learning based applications. In the first set of works, we are exploring learning algorithms and acceleration techniques on graph learning algorithms. At their core, they deal with sparse...

In the era of big data, many applications present siginificant compuational challenges. For example, in the field of bio-infomatics, the computation demand for personalized cancer treatment is prohibitively high for the general-purpose computing technologies, as tumor heterogeneity...

To meet ever-increasing computing needs and overcome power density limitations, the computing industry has entered theera of parallelization, with tens to hundreds of computing cores integrated into a single...

Software Releases

LEKO and LEKU Suites [GitHub]

(Logic synthesis Examples with Known Optimal/Upper-bounds)

Director : ...

Optimal Layout Synthesizer of Quantum Circuits for Dynamically Field-Programmable Qubits Array.