Publications

Books

  1. Y. Xie, J. Cong and S. Sapatnekar, editors. Three-Dimensional Integrated Circuit Design: EDA, Design and Microarchitectures. Springer Publishers, 2009.
  2. G.-J. Nam and J. Cong, editors. Modern Circuit Placement. Springer Publishers, 2007.
  3. J. Cong and J. Shinnerl, editors. Multilevel Optimization in VLSICAD. Kluwer Academic Publishers, 2003.
  4. R. Liberskind-Hadas, N. Hasan, J. Cong, P. Mckinley and C. L. Liu. Fault Covering Problems in Reconfigurable VLSI Systems. Kluwer Academic Publishers, 1992.

Book chapters

  1. J. Cong and G. Luo, "Thermal-Aware 3D Placcement,". Three-Dimensional Integrated Circuit Design: EDA, Design and Microarchitectures. ed. Y. Xie, J. Cong and S. Sapatnekar, Springer Publishers, 2009.
  2. J. Cong and Y. Ma, "Thermal-Aware 3D Floorplan,". Three-Dimensional Integrated Circuit Design: EDA, Design and Microarchitectures. ed. Y. Xie, J. Cong and S. Sapatnekar, Springer Publishers, 2009.
  3. Z. Zhang, Y. Fan, W. Jiang, G. Han, C. Yang, and J. Cong, "AutoPilot: A Platform-Based ESL Synthesis System,". High-Level Synthesis: From Algorithm to Digital Circuit. ed. P. Coussy and A. Morawiec, Springer Publishers, 2008.
  4. T. F. Chan, J. Cong, J. Shinnerl, K. Sze, and M. Xie, "mPL6: Enhancement Multilevel Mixed-Size Placement with Congestion Control,". Modern Circuit Placement. ed. G.-J. Nam and J. Cong, Springer Publishers, 2007, pp. 247-288.
  5. J. Cong, M. Romesis, J. Shinnerl, K. Sze, and M. Xie, "Locality and Utilization in Placement Suboptimality ,". Modern Circuit Placement. ed. G.-J. Nam and J. Cong, Springer Publishers, 2007, pp.13-36.
  6. J. Cong and P. Pan, "Technology Mapping,". Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation (Systems on Silicon). ed. S. Hauck and A. DeHon, Morgan Kaufmann, 2007, pp. 277-296.
  7. J. Cong and J.R. Shinnerl, "Large-Scale Global Placement,". Approximation Algorithms and Metaheuristics. CRC Press, 2006, pp. 79-1--79-19.
  8. T. F. Chan, J. Cong, J. Shinnerl, K. Sze, M. Xie and Y. Zhang. Multiscale Optimization in VLSI Physical Design Automation. Springer Publishers, 2005, pp. 1-68.
  9. J. Cong, M. Xie, and Y. Zhang, "Multilevel VLSI Routing,". Multilevel Optimization in VLSICAD. ed. J. Cong and J. Shinnerl, Kluwer Academic Publishers, 2003, pp. 195-217.
  10. T. F. Chan, J. Cong, T. Kong, and J. Shinnerl, "Multilevel Circuit Planning,". Multilevel Optimization in VLSICAD. ed. J. Cong and J. Shinnerl, Kluwer Academic Publishers, 2003, pp. 155-193.
  11. J. Cong, "Interconnect Planning". Layout Optimization in VLSI Design. ed. B. Lu, D.-Z. Du and S. S. Sapatnekar, Network Theory and Applications Series, Kluwer Academic Publishers, 2001, pp. 19-44.
  12. J. Cong, L. He and C. K. Koh,"Layout Optimization,". Low Power Design in Deep Submicron Electronics. ed. W. Nebel and J. Mermet, NATO ASI Series, Kluwer Academic Publishers, 1997, pp. 205-266.

Journal publications

  1. Anpeng Huang, Wenyao Xu, Zhinan Li, Linzhen Xie, Majid Sarrafzadeh, Xiaoming Li, and Jason Cong. System Light-Loading Technology for mHealth: Manifold-Learning-Based Medical Data Cleansing and Clinical Trials in WE-CARE Project. IEEE Journal of Biomedical and Health Informatics, vol. 18, no. 5, pp. 1581-1589, September 2014.
  2. Jason Cong, Henry Duwe, Rakesh Kumar, and Sen Li. Better-Than-Worst-Case Design: Progress and Opportunities. Journal of Computer Science and Technology, 29(4): 656–663 July 2014.
  3. J. Cong, M. A. Ghodrat, M. Gill, B. Grigorian, G. Reinman. Architecture Support for Domain-Specific Accelerator-Rich CMPs. ACM Transactions on Embedded Computing Systems (TECS), Volume 13, Issue 4s, Article No. 131, April 2014.
  4. Y. Kim, L. Nan, J. Cong, M-C.F. Chang. High-Speed mm-Wave Data-Link Based on Hollow Plastic Cable and CMOS Transceiver. IEEE Microwave and Wireless Components Letters (MWCL), Volume 23, Issue 12, pp. 674-676, December 2013.
  5. Hugh T. Blair, Allan Wu and Jason Cong. Oscillatory neurocomputing with ring attractors: a network architecture for mapping locations in space onto patterns of neural synchrony. Philosophical Transactions of the Royal Society B 2014 369, 20120526, 23 December 2013.
  6. M. Yan, A. Bui, J. Cong and L.A. Vese. General Convergent Expectation Maximization (EM)-Type Algorithms for Image Reconstruction. Inverse Problems and Imaging, Volume 7, Issue 3, pp. 1007-1029, September 2013.
  7. J. Cong and B. Xiao. FPGA-RPI: A Novel FPGA Architecture With RRAM-Based Programmable Interconnects. IEEE Transaction on Very Large Scale Integration (VLSI) Systems, Volume PP, Issue 99, pp. 1-14, May 2013.
  8. G. Luo, Y. Shi and J. Cong. An Analytical Placement Framework for 3-D ICs and Its Extension on Thermal Awareness. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 32, Number 4, pp. 510-523, April 2013.
  9. A. Agarwal, J. Cong and B. Tagiku. The Survivability of Design-Specific Spare Placement in FPGA Architectures with High Defect Rates. ACM Transactions on Design Automation of Electronic Systems, Volume 18, Number 2, Article No. 33, March 2013.
  10. C. Xiao, M.F. Chang, J. Cong, M. Gill, Z. Huang, C. Liu, G. Reinman and H. Wu. Stream Arbitration: Towards Efficient Bandwidth Utilization for Emerging On-Chip Interconnects. ACM Transactions on Architecture and Code Optimization, Article No. 60, Volume 9, Number 4, January 2013.
  11. J. Chen, J. Cong, L.A. Vese, J. Villasensor, M. Yan and Y. Zou. A Hybrid Architecture for Compressive Sensing 3-D CT Reconstruction. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Volume 2, Issue 3, pp. 616-625, September 2012.
  12. K. Therdsteerasukdi, G. Byun, J. Ir, G. Reinman, J. Cong and M.F. Chang. Utilizing Radio-Frequency Interconnect for a Many-DIMM DRAM System. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Volume 2, Issue 2, pp. 210-227, June 2012.
  13. Y. Kim, S.-W. Tam, G.-S. Byun, H. Wu, L. Nan, G. Reinman, J. Cong and M.F. Chang. Analysis of Noncoherent ASK Modulation-Based RF-Interconnect for Memory Interface. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Volume 2, Issue 2, pp. 200-2-09, June 2012.
  14. J. Zhang, X. Liu, M. Tan, X. Cheng and J. Cong. Automatic Instruction-set Extension for Bitwise Operation-Intensive Applications. Chinese Journal of Electronics, Volume 40, Issue 2, pp. 209-214, February 2012.
  15. J. Cong, K. Gururaj, P. Zhang and Y. Zou. Task-level data model for hardware synthesis based on concurrent collections. Journal of Electrical and Computer Engineering - Special issue on ESL Design Methodology, Volume 2012, January 2012.
  16. K. Therdsteerasukdi, G.S. Byun, J. Cong, M.F. Chang and G. Reinman. Utilizing RF-I and Intelligent Scheduling for Better Throughput/Watt in a Mobile GPU Memory System. ACM's Transactions on Architecture and Code Optimization, Volume 8, Issue 4, Article 51, January 2012.
  17. J. Kim, H. Choi, S. Yoon, T. Bang, J. Park, C. Jung and J. Cong. An 8M Polygons/s 3-D Graphics SoC With Full Hardware Geometric and Rendering Engine for Mobile Applications. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 19, Number 8, pp. 1490-1495, August 2011.
  18. J. Cong, H. Huang, and W. Jiang. Pattern Mining for Behavioral Synthesis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 30, Issue 6, pp. 939-944, June 2011.
  19. J. Cong, B. Liu, S. Neuendorffer, J. Noguera, K. Vissers and Z. Zhang. High-Level Synthesis for FPGAs: From Prototyping to Deployment. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 30, Number 4, pp. 473-491, April 2011. (Keynote paper) .
  20. J. Cong, V. Sarkar, G. Reinman and A. Bui. Customizable Domain-Specific Computing. IEEE Design and Test of Computers, Volume 28, Number 2, pp. 5-15, March/April 2011.
  21. J. Cong, W. Jiang, B. Liu and Y. Zou. Automatic Memory Partitioning and Scheduling for Throughput and Power Optimization. ACM Transactions on Design Automation of Electronic Systems, Volume 16, Number 2, Article 15, pp. 1-25, March 2011. ACM (Best Paper Award).
  22. J. Cong, B. Liu, R. Majumdar and Z. Zhang. Behavior-Level Observability Analysis for Operation Gating in Low-Power Behavioral Synthesis. ACM Transactions on Design Automation of Electronic Systems, Volume 16, Number 1, Article 4, pp. 1-29, November 2010. (2012 Best Paper Award of the ACM Transactions on Design Automation of Electronic Systems) .
  23. J. Cong, J. Lee and P. Gupta. Evaluating Statistical Power Optimization. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 29, Number 11, pp. 1750-1762, November 2010.
  24. D. Chen, J. Cong, C. Dong, L. He, F. Li and C. Peng. Technology Mapping and Clustering for FPGA Architectures with Dual Supply Voltages. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 29, Number 11, pp. 1709-1721, November 2010.
  25. R. Brayton and J. Cong. NSF Workshop on EDA: Past, Present, and Future (Part 2). IEEE Design and Test of Computers, Volume 27, Number 3, pp. 62-74, May/June 2010.
  26. R. Brayton and J. Cong. NSF Workshop on EDA: Past, Present, and Future (Part 1). IEEE Design and Test of Computers, Volume 27, Number 2, pp. 68-74, March/April 2010.
  27. J. Cong and G. Luo. Advances and Challenges in 3D Physical Design. IPSJ Transactions on System LSI Design Methodology, Volume 3, pp. 2-18, Feburary 2010. (Invited paper).
  28. J. Cong, K. Gururaj, G. Han, and W. Jiang. Synthesis Algorithm for Application-Specific Homogeneous Processor Networks. IEEE Transaction on Very Large Scale Integration (VLSI) Systems, Volume 17, Number 9, pp.1318-1329, September 2009.
  29. J. Cong and Y. Zou. FPGA-Based Hardware Acceleration of Lithographic Aerial Image Simulation. ACM Transaction on Reconfigurable Technology and Systems, Volume 2, Number 3, pp.17:1-17:29, September 2009.
  30. D. Chen, J. Cong, Y. Fan and L. Wan. LOPASS: A Low-Power Architectural Synthesis System for FPGAs With Interconnect Estimation and Optimization. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 18, Number 4, pp. 564-577, June 2009.
  31. J. Cong, Y. Fan, and J. Xu. Simultaneous Resource Binding and Interconnection Optimization Based on a Distributed Register-File Microarchitecture. ACM Transactions on Design Automation of Electronic Systems, Volume 14, Number 3, Article 35, pp.35:1-35:31, May 2009.
  32. J. Cong, G. Luo, and E. Radke. Highly Efficient Gradient Computation for Density-Constrained Analytical Placement. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 27, Number 12, pp. 2133-2144, December 2008.
  33. Y. Ma, Y. Liu, E. Kursun, G. Reinman, and J. Cong. Investigating the Effects of Fine-Grain Three-Dimensional Integration on Microarchitecture Design. Journal on Emerging Technologies in Computing Systems, Volume 4, Number 4, pp.17:1-17:30, October 2008.
  34. J. Cong and M. Xie. A Robust Mixed-Size Legalization and Detailed Placement Algorithm. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 27, Number 8, pp. 1349-1362, August 2008.
  35. J. Cong, G. Han, A. Jagannathan, G. Reinman, and K. Rutkowski. Accelerating Sequential Applications on CMPs Using Core Spilling. IEEE Transactions on Parallel and Distributed Systems, Volume 18, Number 8, pp. 1094- 1107, August 2007.
  36. C. Li, M. Xie, C. Koh, J. Cong and P. Madden. Routability-Driven Placement and White Space Allocation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 26, Number 5, pp. 858-871, May 2007.
  37. J. Cong and K. Minkovich. Optimality Study of Logic Synthesis for LUT-Based FPGAs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 26, Number 2, pp. 230-239, February 2007.
  38. D. Kirovski, Y.-Y. Hwang, M. Potkonjak and J. Cong. Protecting Combinational Logic Synthesis Solutions. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 25, Issue 12, pp. 2687-2696, Dec. 2006.
  39. D. Chen, J. Cong and P. Pan. FPGA Design Automation: A Survey. Foundations and Trends in Electronic Design Automation, vol. 1, no. 3, pp. 195-330, Nov 2006.
  40. J. Cong, G. Han and Z. Zhang. Architecture and Compiler Optimization for Data Bandwidth Improvement in Configurable Processors. IEEE Transaction on Very Large Scale Integration Systems, Volume 14, Number 9, pp. 986-997, Sept. 2006.
  41. J. Cong, M. Romesis and J.R. Shinnerl. Fast Floorplanning by Look-Ahead Enabled Recursive Bipartitioning. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 25, Issue 9, pp. 1719 - 1732, Sept. 2006.
  42. G. Chen and J. Cong. Simultaneous Placement with Clustering and Duplication. ACM Transaction on Design Automation of Electronic Systems, vol. 11, no. 3, pp. 740-772, July 2006.
  43. D. Chen, J. Cong, and J. Xu. Optimal Simultaneous Module and Multi-Voltage Assignment for Low Power. ACM Transaction on Design Automation of Electronic Systems, vol. 11, Issue 2, pp. 362-386, April 2006.
  44. F. Li, Y. Lin, L. He, D. Chen, and J. Cong. Power Modeling and Characteristics of Field Programmable Gate Arrays. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, Issue 11, pp. 1712-1724, November 2005.
  45. J. Cong, T. Kong, J. Shinnerl, M. Xie, and X. Yuan. Large Scale Circuit Placement. ACM Transaction on Design Automation of Electronic Systems, vol. 10, no. 2, pp. 389-430, April 2005.
  46. J. Cong, J. Fang, M. Xie, and Y. Zhang. MARS - A Multilevel Full-Chip Gridless Routing System. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 3, pp. 382-394, March 2005.
  47. J. Cong, H. Huang, and X. Yuan. Technology Mapping and Architecture Evaluation for k/m-Macrocell-based FPGAs. TODAES, vol. 10, pp. 3 - 23, January 2005 (2005 Best Paper Award of the ACM Transactions on Design Automation of Electronic Systems).
  48. J. Cong, and S. Lim. Retiming-based Timing Analysis With An Application to Mincut-based Global Placement. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 12, pp. 1684 - 1692, December 2004.
  49. J. Cong, Y. Fan, G. Han, X. Yang, and Z. Zhang. Architecture and Synthesis for On-Chip Multi-Cycle Communication. IEEE Transactions on Computer-Aided Design of Integrate d Circuits and Systems, pp.550 - 564, April 2004.
  50. C.-C. Chang, J. Cong, M. Romesis, and M. Xie. Optimality and Scalability Study of Existing Placement Algorithms. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp.537 - 549, April 2004.
  51. D. Chen, J. Cong, M. Ercegovac, and Z. Huang. Performance-driven Mapping for CPLD Architectures. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 10, pp. 1424-1431, October 2003.
  52. J. Cong, and S. K. Lim. Edge Separability-Based Circuit Clustering With Application to Multi-level Circuit Partitioning. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp . 346-357, July 2003.
  53. C.-C. Chang, J. Cong, D. Pan, and X. Yuan. Multilevel Global Placement with Congestion Control. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 4, pp. 395-409, April 2003 .
  54. T. Uchino and J. Cong. An Interconnect Energy Model Considering Coupling Effects. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 7, pp. 763-776, July 2002 .
  55. J. Cong and Z. Pan. Wire Width Planning For Interconnect Performance Optimization. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 3, pp.319-329, March 2002. .
  56. J. Cong, C. K. Koh and P. H. Madden. Interconnect layout Optimization Under Higher Order RLC Model for MCM Designs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 12, pp.1455-1463, December 2001 .
  57. J. Cong, T. Kong and Z. Pan. Buffer Block Planning for Interconnect Planning and Prediction. IEEE Transactions on Very Large Scale Integration, vol. 9, no. 6, pp.929-937, December 2001.
  58. J. Cong, L. He, C. K. Koh and Z. Pan. Interconnect Sizing and Spacing with Consideration of Coupling Capacitance. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 9, pp.1164-1169, September 2001.
  59. J. Cong and Y. -Y. Hwang. Boolean Matching for LUT-Based Logic Blocks With Applications to Architecture Evaluation and Technology Mapping. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 9, pp.1077-1090, September 2001.
  60. J. Cong and Z. (D.) Pan. Interconnect Performance Estimation Models for Design Planning. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 739--752, vol. 20, no. 6, June 2001.
  61. J. Cong, J. Fang and K. -Y. Khoo. DUNE - A Multilayer Gridless Routing System. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, (no. 5), pp 633-647, May 2001.
  62. C.-C. Chang and J. Cong. Pseudopin Assignment with Crosstalk Noise Control. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 5, pp. 598-611, May 2001.
  63. J. Cong. An Interconnect-Centric Design Flow for Nanometer Technologies. Proceedings of the IEEE, vol. 89, No. 4, pp 505-528, April 2001.
  64. J. Cong and S. Xu. Performance-Driven Technology Mapping for Heterogeneous FPGAs. IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, vol. 19, no. 11, pp. 1268-1281, November 2000.
  65. J. Cong and Y. Hwang. Structural Gate Decomposition for Depth-Optimal Technology in LUT-based FPGA Designs. ACM Trans. on Design Automation of Electronic Systems, vol. 5, no. 2, pp. 193-225, April 2000.
  66. J. Cong, J. Fang and K.Y. Khoo. Via design rule consideration in multi-layer maze routing algorithms. IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, vol. 19, no. 2, pp 215-223, February 2000.
  67. J. Cong and C. Wu. Optimal FPGA Mapping and Retiming with Efficient Initial State Computation. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 11, pp 1595 -1607, November 1999.
  68. C.-C. Chang and J. Cong. An Efficient Approach To Multilayer Layer Assignment With An Application To Via Minimization. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.18, no. 5, p.608-620, May 1999.
  69. J. Cong and L. He. Theory and Algorithm of Local-Refinement-Based Optimization with Application to Device and Interconnect Sizing. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.18, no.4, pp. 406-420, April 1999.
  70. J. Cong, A. B. Kahng and K.-S. Leung. Efficient Algorithms for the Minimum Shortest Path Steiner Arborescence Problem with Applications to VLSI Physical Design. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.17, no. 1, pp. 24-39, January 1999.
  71. J. Cong, A. B. Kahng, C. K. Koh and C.-W. Albert Tsao. Bounded-Skew Clock and Steiner Routing. ACM Trans. on Design Automation of Electronic Systems, vol. 3, pp. 341-388, 1998.
  72. J. Cong and C. Wu. An Efficient Algorithm for Performance Optimal FPGA Technology Mapping with Retiming. IEEE Trans. on Computer-Aided Design of Integrated Circuits And Systems vol. 17, no. 9, pp. 738-748, 1998.
  73. J. Cong and P. Madden. Performance-Driven Routing with Multiple Sources. IEEE Trans. on Computer-Aided Design, vol. 16, pp. 410-419, April 1997.
  74. T.C. Lee and J. Cong. The New Line in IC Design. IEEE Spectrum, pp. 52-58, March 1997.
  75. J. Cong and L. He. Optimal Wiresizing for Interconnects with Multiple Sources. ACM Transaction on Design Automation of Electronic Systems, vol. 1, no. 4, pp. 478-511, October 1996.
  76. J. Cong, L. He, C. K. Koh and P. Madden. Performance Optimization of VLSI Interconnect Layout. Integration, the VLSI Journal, vol. 21, pp. 1-94, 1996.
  77. L. Kleinrock, M. Gerla, N. Bambos, J. Cong, E. Gafni, L. Bergman, J. Bannister, S. Monacos, T. Bujewski, P. C. Hu, B. Kannan, B. Kwan, E. Leonardi, J. Peck, P. Palnati, and S. Walton. The Supercomputer Supernet Testbed: A WDM-Based Supercomputer Interconnect. Journal of Lightwave Technology, vol. 14, no. 6, pp. 1388-1399, June 1996.
  78. J. Cong and Y. Ding. Combinational Logic Synthesis for LUT Based Field Programmable Gate Arrays. ACM Trans. on Design Automation of Electronic Systems, vol. 1, no. 2, pp. 145-204 April 1996.
  79. J. Cong, W. J. Labio, and N. Shivkumar. Multiway VLSI Circuit Partitioning Based on Dual net Representation. IEEE Trans. on Computer-Aided Design, vol. 15, no. 4, pp. 396-409, April 1996.
  80. J. Cong and K. Y. Khoo. An Efficient Multilayer MCM Router Based on Four-Via Routing. EEE Trans. on Computer-Aided Design, vol. 14, no. 10, pp. 1277-1290, October 1995.
  81. J. Cong and K. S. Leung. Optimal Wiresizing Under Elmore Delay Model. IEEE Trans. on Computer-Aided Design, vol. 14, no. 3, pp. 321-336, Mar. 1995.
  82. L. Kleinrock, M. Gerla, N. Bambos, J. Cong, E. Gafni, L. Bergman, and J. Bannister. The Supercomputer Supernet: A Scalable Distributed Terabit Network. Journal of High Speed Networks, vol. 4, no. 4, pp. 407-424, 1995 .
  83. J. Cong and C. K. Koh. Simultaneous Driver and Wire Sizing for Performance and Power Optimization. IEEE Trans. on VLSI Systems, vol. 2, no. 4, pp. 408-425, December 1994.
  84. J. Cong, Y. Ding, T. Gao and K. C. Chen. LUT-Based FPGA Technology Mapping Under Arbitrary Net-Delay Model. Computers and Graphics, vol. 18, no. 4, pp. 507-516, 1994.
  85. Y. Cai, D. F. Wong and J. Cong. Channel Density Minimization by Pin Permutation. VLSI Design: An International Journal of Custom-Chip Design, Simulation, and Testing (Special Issue on Optimization in VLSI Synthesis and Layout), vol. 2, no. 2, pp. 171-183, 1994.
  86. C. J. Alpert, J. Cong, A. B. Kahng, G. Robins and M. Sarrafzadeh. On the Minimum Density Interconnection Tree Problem. VLSI Design: An International Journal of Custom-Chip Design, Simulation, and Testing (Special Issue on Optimization in VLSI Synthesis and Layout), vol. 2, no. 2, pp. 171-183, 1994.
  87. J. Cong and Y. Ding. On Nominal Delay Minimization in LUT-Based FPGA Technology Mapping. Integration: the VLSI Journal, vol. 18, pp. 507-516, 1994.
  88. J. Cong and Y. Ding. On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping. IEEE Trans. on VLSI Systems, vol. 2, no. 2, pp. 137-148, June 1994.
  89. D. Zhou, S. Su, F. Fsui, D. S Gao, and J. Cong. A Simplified Synthesis of Transmission Lines with a Tree Structure. Journal of Analog Integrated Circuits and Signal Processing (Special Issue on High-Speed Interconnects), vol. 5, no. 1, pp. 19-30, January 1994.
  90. J. Cong and Y. Ding. FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs. IEEE Trans. on Computer-Aided Design, vol. 13, no. 1, pp. 1-12, January 1994. (1995 Circuit and System Society Best Paper Award in IEEE Transactions on CAD) .
  91. J. Cong, A. B. Kahng and G. Robins. Matching-Based Methods for High-Performance Clock Routing. IEEE Trans. on Computer-Aided Design, vol. 12, no. 8, pp. 1157-1169, August 1993.
  92. J. Cong, B. Preas and C. L. Liu. Physical Models and Efficient Algorithms for Over-the-Cell Routing in Standard Cell Designs. IEEE Trans. on Computer-Aided Design, vol. 12, no. 5, pp. 723-734, May 1993.
  93. J. Cong, M. Hossain and N. Sherwani. A Provably Good Multilayer Topological Planar Routing Algorithm In IC Layout Designs. IEEE Trans. on Computer-Aided Design, vol. 12, no. 1, pp. 70-78, January 1993.
  94. J. Cong and B. Preas. A New Algorithm for Standard Cell Global Routing. Integration: the VLSI Journal, vol. 14, no. 1, pp. 49-65, November 1992.
  95. K. Y. Khoo and J. Cong. A Fast Multilayer General Area Router for MCM Designs. IEEE Trans. on Circuits & Systems II - Analog & Digital Signal Processing,, vol. 39, no. 11, pp. 841-851, November 1992.
  96. K. C. Chen, J. Cong, Y. Ding, A. Kahng, and P. Trajmar. DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization. IEEE Design & Test of Computers, vol. 9, no. 3, pp. 7-20, September, 1992.
  97. J. Cong, A. Kahng, G. Robins, M. Sarrafzadeh and C. K. Wong. Provably Good Performance-Driven Global Routing. IEEE Trans. on Computer-Aided Design, vol. 11, no. 6, pp. 739-752, June 1992.
  98. J. Cong. Pin Assignment with Global Routing for General Cell Design. IEEE Trans. on Computer-Aided Design, vol. 10, pp. 1401-1412, November 1991.
  99. J. Cong and C. L. Liu. On the k-Layer Planar Subset and Topological Via Minimization Problems. IEEE Trans. on Computer-Aided Design, Vol. 10, pp. 972-981, August 1991.
  100. K. S. The, D. F. Wong and J. Cong. A Layout Modification Approach to Via Minimization. IEEE Trans. on Computer-Aided Design, vol. 10, pp. 536-540, April 1991.
  101. J. Cong and C. L. Liu. On the Over-the-Cell Channel Routing. IEEE Trans. Computer-Aided Design, vol. 9, pp. 408-418, April 1990. (1992 IEEE CAS Outstanding Young Author Award Candidate) .
  102. J. Cong and D. F. Wong. Generating More Compactable Channel Routing Solutions. Integration: the VLSI Journal, vol. 9, pp 199-214, April 1990.
  103. J. Cong, D. F. Wong and C. L. Liu. A New Approach to Three- or Four-Layer Channel Routing. IEEE Trans. Computer-Aided Design, vol. 7, pp 1094-1104, July 1988.

Conference publications

  1. Jason Cong and Bingjun Xiao. Minimizing Computation in Convolutional Neural Networks. Proceedings of the 24th International Conference on Artificial Neural Networks, Hamburg, Germany, September 2014.
  2. Muhuan Huang, Kevin Lim and Jason Cong. A Scalable, High-Performance Customized Priority Queue. Proceedings of the 24th International Conference on Field Programmable Logic and Applications (FPL 2014), Munich, Germany, September 2-4, 2014.
  3. Jian Gong, Tao Wang, Jiahua Chen, Haoyang Wu, Fan Ye, Songwu Lu and Jason Cong. An Efficient and Flexible Host-FPGA PCIe Communication Library. Proceedings of the 24th International Conference on Field Programmable Logic and Applications (FPL 2014), Munich, Germany, September 2-4, 2014.
  4. Jason Cong, Peng Li , Bingjun Xiao, and Peng Zhang. An Optimal Microarchitecture for Stencil Computation Acceleration Based on Non-Uniform Partitioning of Data Reuse Buffers. Design Automation Conference, 2014.
  5. Jason Cong, Mohammad Ali Ghodrat, Michael Gill, Beayna Grigorian, Karthik Gururaj, Glenn Reinman. Accelerator-Rich Architectures: Opportunities and Progresses. Design Automation Conference (DAC 2014).
  6. T. Wang, G. Sun, J. Chen, J. Gong, H. Wu, X. Li, S. Lu and J. Cong. GRT: A Reconfigurable SDR Platform with High Performance and Usability. Proceedings of the 5th International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies (HEART 2014), Sendai Miyagi, Japan, June 2014.
  7. Jason Cong, Hui Huang, Chiyuan Ma, Bingjun Xiao and Peipei Zhou. A Fully Pipelined and Dynamically Composable Architecture of CGRA. Proceedings of the 22nd IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), Boston, Massachusetts, May 2014.
  8. Young-kyu Choi, Jason Cong, and Di Wu. FPGA Implementation of EM Algorithm for 3D CT Reconstruction. Proceedings of the 22nd IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), Boston, Massachusetts, May 2014.
  9. J.Cong, S. Jiang, S. Lin, J. Ouyang, G. Sun, P. Wang, C. Zhang. An Efficient Design and Implementation of LSM-Tree based Key-Value Store on Open-Channel SSD. Proceedings of the 2014 EuroSys Conference in Amsterdam, Netherlands, April 2014.
  10. Jason Cong. From Design to Design Automation. Proceedings of the The International Symposium on Physical Design (ISPD 2014), March 2014.
  11. Jason Cong, Muhuan Huang, Peng Zhang. Combining computation and communication optimizations in system synthesis for streaming applications. International Symposium on Field-Programmable Gate Arrays, FPGA 2014.
  12. Yuxin Wang, Peng Li, Jason Cong. Theory and Algorithm for Generalized Memory Partitioning in High-Level Synthesis. International Symposium on Field-Programmable Gate Arrays, FPGA 2014.
  13. J. Cong and B. Xiao. Optimization of Interconnects Between Accelerators and Shared Memories in Dark Silicon. Proceedings of the 2013 International Conference on Computer-Aided Design (ICCAD 2013), pp. 630-637, November 2013.
  14. H.T. Blair, J. Cong, D. Wu. FPGA Simulation Engine for Customized Construction of Neural Microcircuit. Proceedings of the 2013 International Conference on Computer-Aided Design (ICCAD 2013), pp. 607-614, November 2013.
  15. Yu-Ting Chen, Jason Cong, Mohammad Ali Ghodrat, Muhuan Huang, Chunyue Liu, Bingjun Xiao, Yi Zou. Accelerator-rich CMPs: From concept to real hardware. International Conference on Computer Design (ICCD) 2013.
  16. W. Zuo, P. Li, D. Chen, L-N. Pouchet, S. Zhong and J. Cong. Improving Polyhedral Code Generation for High-Level Synthesis. Proceedings of the International Conference on Hardware/Software Co-design and System Synthesis (CODES+ISSS 2013), pp. 1-10, September-October 2013 (Best Paper Award).
  17. J. Cong, M. Ercegovac, M. Huang, S. Li and B. Xiao. Energy-Efficient Computing Using Adaptive Table Lookup Based on Nonvolatile Memories. Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED 2013), pp. 280 - 285, September 2013.
  18. J. Cong, M.A. Ghodrat, M. Gill, B. Grigorian, H. Huang and G. Reinman. Composable Accelerator-rich Microprocessor Enhanced for Adaptivity and Longevity. Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED 2013), pp. 305-310, September 2013.
  19. J. Cong and B. Xiao. Defect Tolerance in Nanodevice-based Programmable Interconnects: Utilization Beyond Avoidance. Proceedings of the 50th Annual Design Automation Conference (DAC 2013), Austin, TX, Article 9, May-June 2013.
  20. A. Papakonstantinou, D. Chen, W-M. Hu, J. Cong and Y. Liang. Throughput-Oriented Kernel Porting onto FPGAs. Proceedings of the 50th Annual Design Automation Conference (DAC 2013), Austin, TX, Article 11, May-June 2013.
  21. Y. Wang, P. Li, P. Zhang, C. Zhang and J. Cong. Memory Partitioning for Multidimensional Arrays in High-Level Synthesis. Proceedings of the 50th Annual Design Automation Conference (DAC 2013), Austin, TX, Article 12, May-June 2013.
  22. P. Wang, G. Sun, T. Wang, Y. Xie and J. Cong. Designing Scratchpad Memory Architecture with Emerging STT-RAM Memory Technologies. Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS 2013), Beijing, China, May 2013.
  23. L.-N. Pouchet, P. Zhang, P. Sadayappan and J. Cong. Polyhedral-Based Data Reuse Optimization for Configurable Computing. Proceedings of the 21st ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2013), Monterey, California, pp. 29-38, February 2013.
  24. Z. Wei, Y. Liang, K. Rupnow, P. Li, D. Chen and J. Cong. Improving High Level Synthesis Optimization Opportunity through Polyhedral Transformations. Proceedings of the 21st ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2013), Monterey, California, pp. 9-18, February 2013.
  25. J. Cong and K. Gururaj. Architecture Support for Custom Instructions with Memory Operations. Proceedings of the 21st ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2013), Monterey, California, pp. 231-234, February 2013.
  26. C. Xiao, M.F. Chang, J. Cong, M. Gill, Z. Huang, C. Liu, G. Reinman and H. Wu. Stream Arbitration: Towards Efficient Bandwidth Utilization for Emerging On-Chip Interconnects. Proceedings of the 8th International Conference on High Performance Embedded Architectures & Compilers (HiPEAC 2013), Berlin, Germany, January 2013.
  27. J. Cong, G. Luo, K. Tsota and B. Xiao. Optimizing Routability in Large-Scale Mixed-Size Placement. Proceedings of the 18th Asia and South Pacific Design Automation Conference (ASPDAC 2012), Yokohama, Japan, January 2013.
  28. P. Li, Y. Wang, P. Zhang, G. Luo, T. Wang and J. Cong. Memory Partitioning and Scheduling Co-optimization in Behavioral Synthesis. Proceedings of the 2012 International Conference on Computer-Aided Design (ICCAD 2012), San Jose, California, pp. 488-495, November 2012.
  29. H. Wu, L. Nan, S.-W. Tam, H.-H. Hsieh, C. Jou, G. Reinman, J. Cong, and M.-C. F. Chang. A 60GHz On-Chip RF-Interconnect with λ/4 Coupler for 5Gbps Bi-Directional Communication and Multi-Drop Arbitration. Proceedings of IEEE Custom Integrated Circuits Conference (CICC 2012), San Jose, California, September 2012.
  30. J. Cong and B. Yuan. Energy-Efficient Scheduling on Heterogeneous Multi-core Architectures. Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED 2012), Redondo, California, pp. 345-350, July-August 2012.
  31. Y. Chen, J. Cong, H. Huang, C. Liu, R. Prabhakar and G. Reinman. Static and Dynamic Co-Optimizations for Blocks Mapping in Hybrid Caches. Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED 2012), Redondo, California, pp. 237-242, July-August 2012.
  32. J. Cong, M.A. Ghodrat, M. Gill, C. Liu and G. Reinman. BiN: A Buffer-in-NUCA Scheme for Accelerator-Rich CMPs. Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED 2012), Redondo, California, pp. 225-230, July-August 2012.
  33. J. Cong, M.A. Ghodrat, M. Gill, B. Grigorian and G. Reinman. CHARM: A Composable Heterogeneous Accelerator-Rich Microprocessor. Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED 2012), Redondo, California, pp. 379-384, July-August 2012.
  34. A. Sbirlea, Y. Zou, Z. Budimlic, J. Cong and V. Sarkar. Mapping a data-flow programming model onto heterogeneous platforms. Proceedings of the 13th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, Tools and Theory for Embedded Systems (LCTES 2012), Beijing, China, pp. 61-70, June 2012.
  35. J. Cong and B. Liu. A Metric for Layout-Friendly Microarchitecture Optimization in High-Level Synthesis. Proceedings of the 49th Annual Design Automation Conference (DAC 2012), San Francisco, CA, pp. 1239-1244, June 2012.
  36. J. Cong, P. Zhang and Y. Zou. Optimizing Memory Hierarchy Allocation with Loop Transformations for High-Level Synthesis. Proceedings of the 49th Annual Design Automation Conference (DAC 2012), San Francisco, CA, pp. 1233-1238, June 2012.
  37. J. Cong, M.A. Ghodrat, M. Gill, B. Grigorian and G. Reinman. Architecture Support for Accelerator-Rich CMPs. Proceedings of the 49th Annual Design Automation Conference (DAC 2012), San Francisco, CA, pp. 843-849, June 2012.
  38. J. Cong, B. Liu, G. Luo and R. Prabhakar. Towards Layout-Friendly High-Level Synthesis. Proceedings of the International Symposium on Physical Design (ISPD 2012), Napa, CA, pp. 165-172, March 2012 (Invited paper).
  39. J. Cong. Transformation from Ad Hoc EDA to Algorithmic EDA. Proceedings of the International Symposium on Physical Design (ISPD 2012), Napa, CA, pp. 57-62, March 2012 (Invited paper).
  40. J. Cong, M. Huang, B. Liu, P. Zhang and Y. Zou. Combining Module Selection and Replication for Throughput-Driven Streaming Programs. Proceedings of Design, Automation and Test in Europe (DATE 2012), Dresden, Germany, March 2012.
  41. Y. Chen, J. Cong, H. Huang, B. Liu, C. Liu, M. Potkonjak and G. Reinman. Dynamically Reconfigurable Hybrid Cache: An Energy-Efficient Last-Level Cache Design. Proceedings of Design, Automation and Test in Europe (DATE 2012), Dresden, Germany, March 2012.
  42. J. Chen, J. Cong, M. Yan and Y. Zou. FPGA-Accelerated 3D Reconstruction using Compressive Sensing. Proceedings of the 20th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2012), Monterey, CA, pp. 163-166, February 2012.
  43. Y. Kim, G. Byun, A. Tang, C.P. Jou, H.H. Hsieh, G. Reinman, J. Cong and M. F. Chang. An 8Gb/s/pin 4pJ/b/pin Simultaneous Bidirectional Single-T-Line Dual (Base+RF) Band Mobile Memory I/O Interface with Inter-Channel Interference Suppression. IEEE International Solid-State Circuits Conference Digest of Technical papers (ISSCC 2012), San Francisco, CA, pp. 50-52, February 2012.
  44. K. Therdsteerasukdi, G. Byun, J. Cong, M.F. Chang and G. Reinman. Utilizing RF-I and Intelligent Scheduling for Better Throughput/Watt in a Mobile GPU Memory System. Proceedings of the 7th International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC 2012), Paris, France, January 2012.
  45. J. Cong, M.A. Ghodrat, M. Gill, H. Huang, B. Liu, R. Prabhakar, G. Reinman and M. Vitanza. Compilation and Architecture Support for Customized Vector Instruction. Proceedings of the 17th Asia and South Pacific Design Automation Conference (ASPDAC 2012), Sydney, Australia, pp. 652-657, January 2012 (Invited paper).
  46. Y. Wang, P. Zhang, X. Cheng and J. Cong. An Integrated and Automated Memory Optimization Flow for FPGA Behavioral Synthesis. Proceedings of the 17th Asia and South Pacific Design Automation Conference (ASPDAC 2012), Sydney, Australia, pp. 257-262, January 2012.
  47. A. Bui, K. Cheng, J. Cong, L. Vese, Y. Wang, B. Yuan and Y. Zou. Platform Characterization for Domain-Specific Computing. Proceedings of the 17th Asia and South Pacific Design Automation Conference (ASPDAC 2012), Sydney, Australia, pp. 94-99, January 2012 (Invited paper).
  48. J. Cong, P. Zhang and Y. Zou. Combined Loop Transformation and Hierarchy Allocation for Data Reuse Optimization. Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD 2011), San Jose, CA, pp. 185-192, November 2011.
  49. J. Cong and K. Gururaj. Assuring Application-Level Correctness against Soft Errors. Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD 2011), San Jose, CA, pp. 150-157, November 2011.
  50. K. Therdsteerasukdi, G. Byun, J. Ir, G. Reinman, J. Cong and M.F. Chang. The DIMM Tree Architecture: A High Bandwidth and Scalable Memory System. Proceedings of the 2011 IEEE International Conference on Computer Design (ICCD 2011), Amherst, Massachusetts, pp. 388-395, October 2011.
  51. Y. Ming, J. Chen, L.A. Vese, J. Villasenor, A. Bui, and J. Cong. EM+TV Based Reconstruction for Cone-Beam CT with Reduced Radiation. Proceedings of the 7th International Symposium on Visual Computing, Las Vegas, Nevada, pp. 1-10, September 2011 (Lecture Notes in Computer Science, Volume 6938, pp. 1-10).
  52. J. Cong, Y. Huang and B. Yuan. ATree-Based Topology Synthesis for On-Chip Network. Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD 2011), San Jose, CA, pp. 651-658, November 2011.
  53. Y. Chen, J. Cong and G. Reinman. HC-Sim: A Fast and Exact L1 Cache Simulator with Scratchpad Memory Co-Simulation Support. Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2011), Taipei, Taiwan, pp. 295-304, October 2011.
  54. J. Cong, B. Grigorian, G. Reinman and M. Vitanza. Accelerating Vision and Navigation Applications on a Customizable Platform. Proceedings of the 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2011), Santa Monica, CA, pp. 25-32, September 2011.
  55. J. Cong, M. Huang and Y. Zou. Accelerating Fluid Registration Algorithm on Multi-FPGA Platforms. Proceedings of the 21st International Conference on Field Programmable Logic and Applications (FPL 2011), Chania, Crete, Greece, pp. 50-57, September 2011.
  56. J. Cong, K. Gururaj, M. Huang, S. Li, B. Xiao and Y. Zou. Domain-Specific Processor with 3D Integration for Medical Image Processing. Proceedings of the 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2011), Santa Monica, CA, pp. 247-250, September 2011.
  57. J. Cong, K. Gururaj, H. Huang, C. Liu, G. Reinman and Y. Zou. An Energy-Efficient Adaptive Hybrid Cache. Proceedings of International Symposium on Low Power Electronics and Design (ISLPED 2011), Fukuoka, Japan, pp. 67-72, August 2011.
  58. J. Chen, M. Yan, L.A. Vese, J. Villasenor, A. Bui and J. Cong. EM+TV for Reconstruction of Cone-Beam CT with Curved Detectors Using GPU. Proceedings of International Meeting on Fully Three-Dimensional Image Reconstruction in Radiology and Nuclear Medicine, Potsdam, Germany, pp. 363-366, July 2011.
  59. J. Cong and B. Xiao. mrFPGA: A Novel FPGA Architecture with Memristor-Based Reconfiguration. Proceedings of the 7th IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2011), San Diego, CA, pp. 1-8, June 2011.
  60. J. Cong, H. Huang, C. Liu and Y. Zou. A Reuse-Aware Prefetching Algorithm for Scratchpad Memory. Proceedings of the 48th Annual Design Automation Conference (DAC 2011), San Diego, CA, pp. 960-965, June 2011.
  61. J. Cong, G. Luo and Y. Shi. Thermal-Aware Cell and Through-Silicon-Via Co-Placement for 3D ICs. Proceedings of the 48th Annual Design Automation Conference (DAC 2011), San Diego, CA, pp. 405-410, June 2011.
  62. J. Cong, M. Huang and Y. Zou. 3D Recursive Gaussian IIR on GPU and FPGAs, A Case Study for Accelerating Bandwidth-Bounded Applications. Proceedings of the 9th IEEE Symposium on Application Specific Processors (SASP 2011), San Diego, CA, pp. 70-73, June 2011.
  63. J. Cong, J. Lee, and G. Luo. A Unified Optimization Framework for Simultaneous Gate Sizing and Placement under Density Constraints. Proceedings of the 24th IEEE International Symposium on Circuits and Systems (ISCAS 2011), Rio de Janeiro, Brazil, pp. 1207-1210, May 2011.
  64. A. Papakonstantinou, Y. Liang, J.A. Stratton, K. Gururaj, D. Chen, W.M. Hwu and J. Cong. Multilevel Granularity Parallelism Synthesis on FPGAs. Proceedings of 19th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2011), Salt Lake City, UT, pp. 178-185, May 2011. (Best Paper Award).
  65. G-S. Byun, Y. Kim, J. Kim, S-W Tam, H-H. Hsieh, P-Y. Wu, C. Jou, J. Cong, G. Reinman and M-C. F. Chang. An 8.4Gb/s 2.5pJ/b Mobile Memory I/O Interface Using Simultaneous Bidirectional Dual (Base+RF) Band Signaling. IEEE International Solid-State Circuits Conference Digest of Technical papers (ISSCC 2011), San Francisco, CA, pp. 488-490, February 2011.
  66. J. Cong, M. A. Ghodrat, M. Gill, C. Liu, G. Reinman and Y. Zou. AXR-CMP: Architecture Support in Accelerator-Rich CMPs. Proceedings of the 2nd Workshop on SoC Architecture, Accelerators and Workloads (SAW-2) , San Antonio, TX, pp. 19-26, February 2011.
  67. T. Thorolfsson, G. Luo, J. Cong and P D. Franzon. Logic-on-Logic 3D Integration and Placement. Proceedings of the 2nd IEEE International 3D System Integration Conference (3DIC 2010) , Munich, Germany, November 2010.
  68. J. Cong and K. Minkovich. LUT-Based FPGA Technology Mapping for Reliability. Proceedings of the 47th Annual Design Automation Conference (DAC 2010) , Anaheim, CA, pp. 517-522, June 2010.
  69. J. Cong, C. Liu and G. Reinman. ACES: Application-Specific Cycle Elimination and Splitting for Deadlock-Free Routing on Irregular Network-on-Chip. Proceedings of the 47th Annual Design Automation Conference (DAC 2010) , Anaheim, CA, pp. 443-448, June 2010.
  70. J. Cong and Y. Zou. A Comparative Study on the Architecture Templates for Dynamic Nested Loops. Proceedings of the 18th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2010) , Charlotte, NC, pp.251-254, May 2010.
  71. J. Cong and G. Luo. An Analytical Placer for Mixed-size 3D Placement. Proceedings of the International Symposium on Physical Design (ISPD 2010), San Francisco, CA, pp. 61-66, March 2010.
  72. J. Cong, B. Liu, and J. Xu. Coordinated Resource Optimization for Behavioral Synthesis. Proceedings of Design, Automation and Test Europe (DATE 2010), Dresden, Germany, pp. 1267-1272, March 2010.
  73. J. Cong, H. Huang, and W. Jiang. A Generalized Control-Flow-Aware Pattern Recognition Algorithm for Behavior Synthesis. Proceedings of Design, Automation and Test Europe (DATE 2010), Dresden, Germany, pp. 1255-1260, March 2010.
  74. J. Cong, K. Gururaj, W. Jiang, B. Liu, K. Minkovich, B. Yuan and Y. Zou. Accelerating Monte Carlo based SSTA using FPGA. Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA 2010), Monterey, California, pp. 111-114, February 2010.
  75. J. Zhang, Z. Zhang, S. Zhou, M. Tan, X. Liu, X. Cheng and J. Cong. Bit-Level Optimization for High-Level Synthesis and FPGA-Based Acceleration. Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA 2010), Monterey, California, pp. 59-68, February 2010.
  76. J. Cong, W. Jiang, B. Liu, and Y. Zou. Automatic Memory Partitioning and Scheduling for Throughput and Power Optimization. Proceedings of the 2009 International Conference on Computer-Aided Design(ICCAD 2009), San Jose, California, pp. 697-704, November 2009.
  77. J. Cong, and Y. Zou. Parallel Multi-level Analytical Global Placement on Graphics Processing Units. Proceedings of the 2009 International Conference on Computer-Aided Design(ICCAD 2009), San Jose, California, pp. 681-688, November 2009.
  78. T. F. Chan, J. Cong, and E. Radke. A Rigorous Framework for Convergent Net Weighting Schemes in Timing-Driven Placement. Proceedings of the 2009 International Conference on Computer-Aided Design(ICCAD 2009), San Jose, California, pp. 288-294, November 2009.
  79. J. Cong, B. Liu, and Z. Zhang. Scheduling with Soft Constraints. Proceedings of the 2009 International Conference on Computer-Aided Design(ICCAD 2009), San Jose, California, pp. 47-54, November 2009.
  80. J. Cong, A. Liu, and B. Liu. A Variation-Tolerant Scheduler for Better Than Worst-Case Behavioral Synthesis. Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2009), Grenoble, France, pp. 221-228, October 2009.
  81. S-B. Lee, S.-W. Tam, I. Pefkianakis, S. Lu, M. F. Chang, C. Guo, G. Reinman, C. Peng, M. Naik, L. Zhang, and J. Cong. A Scalable Micro Wireless Interconnect Structure for CMPs. ACM MobiCom 2009, Beijing, China, pp. 217-228, September 2009.
  82. J. Zhang, Z. Zhang, S. Zhou, M. Tan, X. Liu, X. Cheng, and J. Cong. Bit-Level Transformation and Optimization for Hardware Synthesis of Algorithmic Descriptions. Proceedings of the 18th International Workshop on Logic & Synthesis (IWLS 2009), Berkeley, California, pp. 119-126, July 31-August 2, 2009.
  83. J. Cong, A. Liu, and B. Liu. A Variation-Tolerant Scheduler for Better Than Worst-Case Behavioral Synthesis. Proceedings of the 18th International Workshop on Logic & Synthesis (IWLS 2009), Berkeley, California, pp. 72-79, July 31-August 2, 2009.
  84. J. Cong, B. Liu, and Z. Zhang. Behavior-Level Observability Dont-Cares and Application to Low-Power Behavioral Synthesis. Proceedings of the International Symposium on Low Power Electronics & Design (ISLPED 2009), San Francisco, California, pp. 139-144, August 2009.
  85. J. Cong, M. F. Chang, G. Reinman, and S.-W. Tam. Multiband RF-Interconnect for Reconfigurable Network-on-Chip Communication. System Level Interconnect Prediction (SLIP 2009), San Francisco California, pp. 107-108, July 2009.
  86. J. Cong and G. Luo. A 3D Physical Design Flow Based on OpenAccess. International Conference on Communications, Circuits and Systems (ICCCAS) San Jose California, pp. 1103-1107, July 2009. (Invited Paper).
  87. A. Papakonstantinou, K. Gururaj, J. A. Stratton, D. Chen, J. Cong, and W. W. Hwu. FCUDA: Enabling Efficient Compilation of CUDA Kernels onto FPGAs. Symposium on Application Specific Processors , pp.35-42, July 2009. (Best Paper Award).
  88. A. Papakonstantinou, K. Gururaj, J. Stratton, D. Chen, J. Cong, W. Hwu. High-Performance CUDA Kernel Execution on FPGAs. ACM/SIGARCH 23rd International Conference on Supercomputing, Metro New York City Area, pp. 515-516, June 2009.
  89. J. Cong and K. Minkovich. Logic Synthesis for Better Than Worst-case Designs. Proceedings International Symposium on VLSI Design, Automation and Test, pp. 166-169, April 2009.
  90. J. Cong, K. Gururaj, B. Liu, C. Liu, Z. Zhang, S. Zhou and Y. Zou. Evaluation of Static Analysis Techniques for Fixed-Point Precision Optimization. Proceedings 17th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2009), Napa, California, pp. 231-234, April 2009.
  91. J. Cong and K. Gururaj. Energy Efficient Multiprocessor Task Scheduling under Input-dependent Variation. Proceedings of Design, Automation and Test in Europe, pp. 411-416, April 2009.
  92. J. Cong, K. Gururaj, and G. Han. Synthesis of Reconfigurable High-Performance Multicore Systems. Proceedings of Field Programmable Gate Arrays, Monterey, California, pp. 201-208, February 2009.
  93. J. Cong and G. Luo. A Multilevel Analytical Placement for 3D ICs. Proceedings of the 14th Asia and South Pacific Design Automation Conference (ASP-DAC 2009), Yokohama, Japan, pp. 361-366, January 2009.
  94. J. Cong, P. Gupta and J. Lee. On the Futility of Statistical Power Optimization. Proceedings of the 14th Asia and South Pacific Design Automation Conference (ASP-DAC 2009), Yokohama, Japan, pp. 167-172, January 2009.
  95. M. F. Chang, J. Cong, A. Kaplan, C. Liu, M. Naik, J. Premkumar, G. Reinman, E. Socher, and R. Tam. Power Reduction of CMP Communication Networks via RFInterconnects. Proceedings of the 41st Annual International Symposium on Microarchitecture (MICRO), Lake ComoItaly pp. 376-387, November 2008.
  96. J. Cong, K. Gururaj, G. Han, A. Kaplan, M. Naik and G. Reinman. MC-Sim: An efficient simulation tool for MPSoC designs. Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design (ICCAD 2008), San Jose, CA, pp. 364-371, November 2008.
  97. A. Agarwal, J. Cong, and B. Tagiku. Fault Tolerant Placement and Defect Reconfiguration for nano-FPGAs. Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design (ICCAD 2008), San Jose, CA, pp. 714-721, November 2008.
  98. J. Cong, C. Liu, and G. Luo. Quantitative Studies of Impact of 3D IC Design on Repeater Usage. Proceedings of 25th International VLSI/ULSI Multilevel Interconnection Conference (VMIC), Fremont, CA, pp. 344-348, October 2008.(Invited Paper).
  99. M.-C. F. Chang, E. Socher, S.-W. Tam, J. Cong, and G. Reinman. RF Interconnects for Communications On-chip. Proceedings of the 2008 ACM International Symposium on Physical Design, Portland, Oregon, pp. 78-83, April 2008. (Invited Paper).
  100. J. Cong and G. Luo. Highly Efficient Gradient Computation for Density-Constrained Analytical Placement Methods. Proceedings of the 2008 ACM International Symposium on Physical Design, Portland, Oregon, pp. 39-46, April 2008.
  101. J. Cong, J. Lee, and L. Vandenberghe. Robust Gate Sizing via Mean Excess Delay Minimization. Proceedings of the 2008 ACM International Symposium on Physical Design, Portland, Oregon, pp. 10-14, April 2008.
  102. J. Cong and J. Xu. Simultaneous FU and Register Binding Based on Network Flow Method. Design, Automation and Test in Europe (DATE 2008), Munich, Germany, pp.1057-1062, March 2008.
  103. J. Cong and Y. Zou. Lithographic Aerial Image Simulation with FPGA-Based Hardware Acceleration. Proc. 16th ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA 2008), Monterey, CA, pp. 20-29, February 2008.
  104. J. Cong and K. Minkovich. Mapping for Better Than Worst-Case Delays In LUT-Based FPGA Designs. Proc. 16th ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA 2008), Monterey, CA, pp. 56-64, February 2008.
  105. J. Cong and W. Jiang. Pattern-based Behavior Synthesis for FPGA Resource Reduction. Proc. 16th ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA 2008), Monterey, CA, pp. 107-116, February 2008.
  106. M. Chang, J. Cong, A. Kaplan, M. Naik, G. Reinman, E. Socher and S.W. Tam. CMP Network-on-Chip Overlaid With Multi-Band RF-Interconnect. The 14th International Symposium on High-Performance Computer Architecture, Salt Lake City, UT, pp. 191-202, February 2008. (Best Paper Award).
  107. X. Li, Y. Ma, X. Hong, S. Dong, and J. Cong. LP Based White Space Redistribution for Thermal Via Planning and Performance Optimization in 3D ICs. Proc. Asia and South Pacific Design Automation Conference (ASP-DAC 2008), pp. 209-212, January 2008.
  108. C.T. Hsieh, J. Cong, Z. Zhang and S.C. Chang. Behavioral Synthesis with Activating Unused Flip-Flops for Reducing Glitch Power in FPGA. Proc. Asia and South Pacific Design Automation Conference (ASP-DAC 2008), pp. 10-15, January 2008.
  109. W. Jiang, Z. Zhang, M. Potkonjak and J. Cong. Scheduling with Integer Delay Budgeting for Low-Power Optimization. Proc. Asia and South Pacific Design Automation Conference (ASP-DAC 2008), pp. 22-27, January 2008.
  110. Y. Liu, Y. Ma, E. Kursun, G. Reinman and J. Cong. Fine Grain 3D Integration for Microarchitecture Design Through Cube Packing Exploration. Proc. IEEE International Conference on Computer Designs, Lake Tahoe, CA, pp. 259-266, October 2007.
  111. J. Cong, Y. Ma, Y. Liu, E. Kursun, and G. Reinman. 3D Architecture Modeling and Exploration. Proceedings of 24th International VLSI/ULSI Multilevel Interconnection Conference (VMIC), Fremont, CA, pages 231-238, September 2007.
  112. J. Cong, and K. Minkovich. Improved SAT-Based Boolean Matching Using Implicants for LUT-Based FPGAs. Proceedings of the 15th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, CA, pp. 139-147, February 2007.
  113. J. Cong, G. Han, and W. Jiang. Synthesis of an Application-Specific Soft Multiprocessor System. Proceedings of the 15th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, CA, pp. 99-107, February 2007.
  114. Y. Ma, Z. Li, J. Cong, X. Hong, G. Reinman, S. Dong, and Q. Zhou. Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning. Proceedings of the 12th Asia and South Pacific Design Automation Conference (ASP-DAC 2007), Yokohama, Japan, pp. 920-925, January 2007.
  115. J. Cong, G. Luo, J. Wei, and Y. Zhang. Thermal-Aware 3D IC Placement via Transformation. Proceedings of the 12th Asia and South Pacific Design Automation Conference (ASP-DAC 2007), Yokohama, Japan, pp. 780-785, January 2007.
  116. D. Chen, J. Cong, Y. Fan, and Z. Zhang. High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs. Proceedings of the 12th Asia and South Pacific Design Automation Conference (ASP-DAC 2007), Yokohama, Japan, pp. 529-534, January 2007.
  117. J. Cong, Y. Fan, and W. Jiang. Platform-Based Resource Binding Using a Distributed Register-File Microarchitecture. Proc. ACM/IEEE International Conference on Computer Aided Design, San Jose, California, pp. 709-715, November 2006.
  118. J. Cong, Y. Fan, G. Han, W. Jiang, and Z. Zhang. Platform-Based Behavior-Level and System-Level Synthesis. Proceedings of IEEE International SOC Conference, pp. 199-202, Austin, Texas, Sept. 2006. (Invited Paper).
  119. J. Cong and Y. Zhang. Thermal-Aware Physical Design Flow for 3-D ICs. Proceedings of the 23rd International VLSI Multilevel Interconnection Conference (VMIC), pp. 73-80, Fremont, CA, September, 2006.
  120. D. Chen, J. Cong, Y. Fan and J. Xu. Optimality Study of Resource Binding with Multi-Vdds. Proceedings of the 2006 Design Automation Conference, San Francisco, CA, pp. 580-585, July 2006.
  121. J.Y. Lin, D. Chen and J. Cong. Optimal Simultaneous Mapping and Clustering for FPGA Delay Optimization. Proceedings of the 2006 Design Automation Conference, San Francisco, CA, pp. 472-477, July 2006.
  122. J. Cong, Y. Fan, G. Han, W. Jiang and Z. Zhang. Behavior and Communication Co-Optimization for Systems with Sequential Communication Media. Proceedings of the 2006 Design Automation Conference, San Francisco, CA, pp. 675-678, July 2006.
  123. J. Cong and Z. Zhang. An Efficient and Versatile Scheduling Algorithm Based On SDC Formulation. Proceedings of the 2006 Design Automation Conference, San Francisco, CA, pp. 433-438, July 2006.
  124. J. Cong, T. Chan, J. Shinnerl, K. Sze and M. Xie. mPL6: Enhanced Multilevel Mixed-size Placement. Proceedings of the ACM International Symposium on Physical Design (ISPD 2006), San Jose, CA, pp. 212-214, April 2006.
  125. J. Cong and K. Minkovich. Optimality Study of Logic Synthesis for LUT-Based FPGAs. Proceedings of the 14th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, CA, pp. 33-40, January 2006.
  126. J. Cong, A. Jagannathan, Y. Ma, G. Reinman and J. Wei. An Automated Design Flow for 3D Microarchitecture Evaluation. Proceedings of the 11th Asia and South Pacific Design Automation Conference (ASP-DAC 2006), Yokohama, Japan, pp.384-389, January 2006.
  127. J. Cong and Min Xie. A Robust Detailed Placement for Mixed-Size IC Designs. Proceedings of the 11th Asia and South Pacific Design Automation Conference (ASP-DAC 2006), Yokohama, Japan, pp. 188-194, January 2006.
  128. J. Cong, M. Romesis and J. Shinnerl. Robust Mixed-Size Placement Under Tight White-Space Constraints. Proceedings of the 2005 IEEE/ACM International Conference on Computer Aided Design, San Jose, CA, pp. 165-172, November 2005.
  129. J. Cong and Y. Zhang. Thermal Via Planning for 3-D ICs. Proceedings of the 2005 IEEE/ACM International Conference on Computer Aided Design, San Jose, CA, pp. 745-752, November 2005.
  130. J. Cong, G. Han and Z. Zhang. Architecture and Compilation for Data Bandwidth Improvement in Configurable Embedded Processors. Proceedings of the 2005 IEEE/ACM International Conference on Computer Aided Design, San Jose, CA, pp. 263-270, November 2005.
  131. J. Cong, A. Jagannathan, G. Reinman and Y. Tamir. Understanding the Energy Efficiency of SMT and CMP with Multiclustering. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, San Diego, CA, pp. 48-53, August 2005.
  132. J. Xu, J. Cong and X. Cheng. Lower-Bound Estimation for Multi-Bitwidth Scheduling. Proceedings of the International Symposium on Circuits and Systems, Kobe, Japan, pp. 856-861, May 2005.
  133. T. Chan, J. Cong, and K. Sze. Multilevel Generalized Force-directed Method for Circuit Placement. Proceedings of the International Symposium on Physical Design, San Francisco, CA, pp. 185-192, April 2005.(Best Paper Award).
  134. G. Chen and J. Cong. Simultaneous Timing-Driven Placement and Duplication. Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, CA, pp. 51-59, February 2005.
  135. J. Cong, Y. Fan, G. Han, A. Jagannathan, G. Reinman and Z. Zhang. Instruction Set Extension with Shadow Registers for Configurable Processors. Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, CA, pp. 99-106, February 2005.
  136. J. Cong, and Y. Zhang. Thermal-Driven Multilevel Routing for 3-D ICs. Proceedings of the Asia South Pacific Design Automation Conference, pp.121-126, January 2005.
  137. J. Cong, Y. Fan, G. Han, Y. Lin, J. Xu, Z. Zhang, and X. Cheng. Bitwidth-Aware Scheduling and Binding in High-Level Synthesis. Proceedings of the Asia South Pacific Design Automation Conference, pp. 856-861, January 2005.
  138. D. Chen, J. Cong, and J. Xu. Optimal Module and Voltage Assignment for Low-Power. Proceedings of the Asia South Pacific Design Automation Conference, pp. 51-59, January 2005.
  139. J. Cong, M. Romesis, and J. Shinnerl. Fast Floorplanning by Look-Ahead Enabled Recursive Bipartitioning. Proceedings of the Asia South Pacific Design Automation Conference, pp. 1119-1122, January 2005.
  140. A. Jagannathan, H. Yang, K. Konigsfeld, D. Milliron, M. Mohan, M. Romesis, G. Reinman, and J. Cong. Micro-Architecture Evaluation with Floorplanning and Interconnect Pipelining. Proceedings of the Asia South Pacific Design Automation Conference, pp. 8-15, January 2005. (invited paper).
  141. J. Cong, J. Wei, and Y. Zhang. A Thermal-Driven Floorplanning Algorithm for 3D ICs. Proceedings of the International Conference on Computer-Aided Design, pp. 306-313, November 2004.
  142. D. Chen, and J. Cong. DAOmap : A Depth-Optimal Area Optimization Mapping Algorithm for FPGA Designs. Proceedings of the International Conference on Computer-Aided Design, pp. 752-759, November 2004.
  143. C. Li, M. Xie, C.K. Koh, J. Cong, and P. Madden. Routability-Driven Placement and White Space Allocation. Proceedings of the International Conference on Computer-Aided Design, pp. 394-401, November 2004.
  144. J. Cong, A. Jagannathan, G. Reinman and Y. Tamir. A Communication-Centric Approach to Instruction Steering For Future Clustered Processors. Proceedings of the First Watson Conference on Interaction between Architecture, Circuits, and Compilers, Yorktown Heights, pp.144-153, NY, October, 2004 (PAC-2).
  145. G. Chen and J. Cong. Simultaneous Timing Driven Clustering and Placement for FPGAs. Proc. International Conference on Field Programmable Logic and its Applications, pp. 158-167, August 2004.
  146. D. Chen, and J. Cong. Delay Optimal Low-Power Circuit Clustering for FPGAs with Dual Supply Voltages. International Symposium on Low Power Electronics and Design, August 2004, pp. 70 - 73.
  147. J. Cong, Y. Fan, and Z. Zhang. Architecture-Level Synthesis for Automatic Interconnect Pipelining. Proceedings of the Design Automation Conference, pp. 602 - 607, June 2004.
  148. J. Cong, G. Nataneli, M. Romesis, and J. Shinnerl. An Area-Optimality Study of Floorplanning. Proceedings of the International Symposium on Physical Design, pp. 78 - 83, April 2004.
  149. D. Chen, J. Cong, F. Li, and L. He. Low-Power Technology Mapping for FPGA Architectures with Dual Supply Voltages. Proceedings of the ACM International Symposium on Field-Programmable Gate Arrays, pp. 109 - 117, February 2004.
  150. J. Cong, Y. Fan, G. Han, and Z. Zhang,. Application-Specific Instruction Generation for Configurable Processor Architectures. Proceedings of the ACM International Symposium on Field-Programmable Gate Arrays, pp. 183 - 189, February 2004.
  151. F. Li, Y. Lin, L. He, and J.Cong. Low-power FPGA using Pre-Defined Dual-Vdd/Dual-Vt Fabrics. Proceedings of the ACM International Symposium on Field-Programmable Gate Arrays, pp. 42 - 50 , February 2004.
  152. D. Chen, and J. Cong. Register Binding and Port Assignment for Multiplexer Optimization. Proceedings of the Asia Pacific Design Automation Conference, pp. 68 - 73, January 2004.
  153. J. Cong, T. Kong, J. Shinnerl, M. Xie and X. Yuan. Large-Scale Circuit Placement. Proceedings of International Conference on Computer Aided Design,, pp. 883-890, November 2003.
  154. T. F. Chan, J. Cong, J. Shinnerl and K. Sze. An Enhanced Multilevel Algorithm for Circuit Placement. Proceedings of International Conference on Computer Aided Design, pp. 299-306, November 2003.
  155. Z. Zhang, Y. Fan, M. Potkonjak and J. Cong. Gradual Relaxation Technique with Application to Behavioral Synthesis. Proceedings of International Conference on Computer Aided Design,, pp. 529-535, November 2003.
  156. J. Cong, Y. Fan, G. Han X. Yang and Z. Zhang. Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication. Proceedings of International Conference on Computer Aided Design,, pp. 536-543, November 2003.
  157. J. Cong, M. Romesis, and M. Xie. Optimality and Stability Study of Timing-driven Placement Algorithms. Proceedings of International Conference on Computer Aided Design,, pp. 472-478, November 2003.
  158. D. Chen, J. Cong, and Y. Fan. Low-Power High-Level Synthesis for FPGA Architectures. 2003 International Symposium on Low Power Electronics and Design, Seoul, Korea, pp. 134 - 139, Aug. 2003.
  159. J. Cong, and X. Yuan. Multilevel Global Placement with Retiming. ACM/SIGDA Proceedings of the 40th Design Automation Conference, Anaheim, California, pp. 208 - 213, June 2003.
  160. J. Cong, A. Jagannathan, G. Reinman and M. Romesis. Microarchitecture Evaluation with Physical Planning. ACM/SIGDA Proceedings of the 40th Design Automation Conference, Anaheim, California, pp. 32 - 35, June 2003.
  161. J. Cong, Y. Fan, X. Yang and Z. Zhang. Architecture and Synthesis for Multi-Cycle Communication. ACM/SIGDA Proceedings of 2003 International Symposium on Physical Design, Monterey, California, pp. 190-196, April 2003.(Invited paper).
  162. J. Cong, M. Romesis and M. Xie. Optimality, Scalability and Stability Study of Partitioning and Placement Algorithms. Proceedings of the International Symposium on Physical Design, Monterey, California, pp. 88 - 94, April 2003.
  163. J. Y. Lin, A. Jagannathan and J. Cong. Placement-Driven Technology Mapping For LUT-Based FPGAs. ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, California, pp. 121 - 126, February 2003.
  164. F. Li, D. Chen, L. He, and J. Cong. Architecture Evaluation for Power-Efficient FPGAs. ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, California, pp. 175 - 184, February 2003.
  165. C.-C. Chang, J. Cong and X. Yuan. Multi-level Placement for Large-Scale Mixed-Size IC Designs. Proc. Asia South Pacific Design Automation Conference, pp. 325-330, January 2003.
  166. C.-C. Chang, J. Cong and M. Xie. Optimality and Scalability Study of Existing Placement Algorithms. Asia South Pacific Design Automation Conference, Kitakyushu, Japan, pp. 621-627, January 2003.
  167. J. Cong, J. Y. Lin and W. Long. A New Enhanced SPFD Rewiring Algorithm. Proc. IEEE International Conference on Computer Aided Design, San Jose, California, pp. 672-678, November 2002 .
  168. J. Cong, M. Xie and Y. Zhang. An Enhanced Multilevel Routing System. Proc. IEEE International Conference on Computer Aided Design, San Jose, California, pp. 51-58, November 2002.
  169. J. Cong, J. Y. Lin and W. Long. Enhanced SPFD Rewiring on Improving Rewiring Ability. IWLS, pp. 91 - 96, June 2002 .
  170. J. Cong. Timing Closure Based on Physical Hierarchy. Proc. International Symposium on Physical Design, San Diego, California, pp. 170-174, April 2002. (Invited paper).
  171. J. Cong, and C. Wu. Global Clustering-Based Performance-Driven Circuit Partitioning. Proc. International Symposium on Physical Design, San Diego, California, pp. 149-154, April 2002.
  172. C-C. Chang, J. Cong, Z. Pan and X. Yuan. Physical Hierarchy Generation with Routing Congestion Control. Proc. International Symposium on Physical Design, San Diego, California, pp. 36-41, April 2002.
  173. J. Cong, Y. Lin and W. Long. SPFD-Based Global Rewiring. Proc. ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, California, pp. 77-84, February 2002.
  174. J. Cong, J. Fang and Y. Zhang. Multilevel Approach to Full-Chip Gridless Routing. Proc. IEEE International Conference on Computer Aided Design, San Jose, California, pp. 396-403, November 2001.
  175. J. Cong. An Interconnect-Centric Design Flow for Nanometer Technologies. Procedings of the Workshop on Synthesis And System Integration of Mixed Technologies, pp. 199 - 205, October 2001. (Invited paper).
  176. C. Chang, J. Cong, T. Uchinko and X. Yuan. Power Model for Interconnect Planning. Procedings of the Workshop on Synthesis And System Integration of Mixed Technologies, pp. 234 - 241, October 2001.
  177. J. Cong and W. Long. SPFD-Based Global Rewiring. 10th International Workshop on Logic & Synthesis, pp. 150-155, June 2001.
  178. J. Cong and T. Uchinko. An Interconnect Energy Model Considering Coupling Effects. Proceedings of the 38th Design Automation Conference, pp. 555-558, June 2001.
  179. J. Cong and M. Romesis. Performance-Driven Multi-Level Clustering with Application to Hierarchical FPGA Mapping. Proceedings of the Design Automation Conference, pp. 389-394, Las Vegas, Nevada, June 2001.
  180. J. Cong, D. Z. Pan and P. V. Srinivas. Improved Crosstalk Modeling for Noise Constrained Interconnect Optimization. Proc. Asian and South Pacific Design Automation Conference (ASPDAC), pp. 373-378, Pacifico Yokohama, Japan, 2001.
  181. G. Chen and J. Cong. Simultaneous Logic Decomposition with Technology Mapping in FPGA Designs. Proc. ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, California, pp. 48-55, February 2001.
  182. D. Chen, J. Cong, M. Ercegovac and Z. Huang. Performance-Driven Mapping for CPLD Architecture. Proc. ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, California, pp. 39-47, February 2001.
  183. J. Cong, D. Z. Pan and P. V. Srinivas. Improved Crosstalk Modeling for Noise Constrained interconnect Optimization. ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, pp. 14-20, Austin, December 2000.
  184. O. Goundert, J. Cong, S. Malik and M. Sarrafzadeh. Incremental CAD. Proc. IEEE International Conference on Computer Aided Design, San Jose, California, pp. 236-243, November 2000.
  185. T. Chan, J. Cong, T. Kong and J. Shinnerl. Multilevel Optimization for Large-scale Circuit Placement. Proc. IEEE International Conference on Computer Aided Design, San Jose, California, pp. 171-176, November 2000.
  186. J. Cong and S. K. Lim. Physical Planning with Retiming. Proc. IEEE International Conference on Computer Aided Design, San Jose, California, pp. 2-7, November 2000.
  187. J. Cong, H. Huang, Yean-Yow Hwang, C. Wu and S. Xu. fpgaEva: A Logic-Level Architecture Evaluator for SRAM-Based FPGAs. Proc. of 16th IFIP World Computer Congress - ICDA'2000: Chip Design Automation, Beijing, P.R. China, pp. 179-184, August 2000.
  188. J. Cong and X. Yuan. Routing Tree Construction Under Fixed Buffer Locations. Proc. ACM/IEEE 37th Design Automation Conference, Los Angeles, California, pp. 379-384, June 2000.
  189. J. Cong and H. Huang. Depth Optimal Incremental Mapping for Field Programmable Gate Arrays. Proc. ACM/IEEE 37th Design Automation Conference, , Los Angeles, California, pp. 290-293, June 2000.
  190. J. Cong, S. K. Lim and Chang Wu. Performance Driven Multi-level and Multiway Partitioning With Retiming. Proc. ACM/IEEE 37th Design Automation Conference, , Los Angeles, California, pp. 274-279, June 2000.
  191. C.-C. Chang and Jason Cong. Pseudo Pin Assignment with Crosstalk Noise Control. Proc. International Symposium on Physical Design, , San Diego, California, pp. 41-47, April 2000.
  192. J. Cong, J. Fang and K.-Y. Khoo. DUNE: A Multi-Layer Gridless Routing System with Wire Planning. Proc. International Symposium on Physical Design, , San Diego, California, pp. 12-18, April 2000.
  193. J. Cong and M. Sarrafzadeh. Incremental Physical Design. Proc. International Symposium on Physical Design, , San Diego, California, pp. 84-92, April 2000.
  194. J. Cong and K. Yan. Synthesis for FPGAs with Embedded Memory Blocks. Proc. ACM/SIGDA International Symposium on Field Programmable Gate Arrays, San Jose, California, Feb. 2000, pp. 75-82, February 2000.
  195. J. Cong, H. Huang and X. Yuan. Technology Mapping for k/m-macrocell Based FPGAs. Proc. ACM/SIGDA International Symposium on Field Programmable Gate Arrays, San Jose, California, pp. 51-59, February 2000.
  196. M. Wang, S. K. Lim, J. Cong and M. Sarrafzadeh. Multi-way Partitioning Using Bi-partition Heuristics. Asia South Pacific Design Automation Conference, Yokohama Japan, pp. 667-672, January 2000.
  197. J. Cong and S. K. Lim. Performance Driven Multiway Partitioning. Asia South Pacific Design Automation Conference, Yokohama Japan, pp. 441-446, January 2000.
  198. J. Cong and S. K. Lim. Edge Separability based Circuit Clustering With Application to Circuit Partitioning. Asia South Pacific Design Automation Conference, Yokohama Japan, pp. 429-434, January 2000.
  199. J. Cong and Songjie Xu. Synthesis Challenges for Next-Generation High-Performance and High-Density PLDs. Asia and South Pacific Design Automation Conference, Yokohama, Japan, pp. 157-162, January 2000. (Invited Talk).
  200. J. Cong, T. Kong and D.Z. Pan. Buffer Block Planning for Interconnect-Driven Floorplanning. Proc. ACM/IEEE International Conference on Computer Aided Design, San Jose, California, pp. 358-363, November 1999.
  201. J. Cong, J. Fang and K.Y. Khoo. An Implicit Connection Graph Maze Routing Algorithm for ECO Routing. Proc. ACM/IEEE International Conference on Computer Aided Design, San Jose, California, pp. 163-167, November 1999.
  202. J. Cong and D.Z. Pan. Interconnect Estimation and Planning for Deep Submicron Designs. Proc. 36th ACM/IEEE Design Automation Conf., New Orleans, Louisiana, pp. 507-510, June 1999.
  203. J. Cong, H. Li and C. Wu. Simultaneous Circuit Partitioning/Clustering with Retiming for Performance Optimization. Proc. 36th ACM/IEEE Design Automation Conf., New Orleans, Louisiana, pp. 460-465, June 1999.
  204. J. Cong, Y.-Y. Hwang and Songjie Xu. Technology Mapping for FPGAs with Nonuniform Pin Delays and Fast Interconnections. Proc. 36th ACM/IEEE Design Automation Conf., New Orleans, Louisiana, pp. 373-378, June 1999.
  205. J. Cong. An Interconnect-Centric Design Flow for Nanometer Technologies. Proc. of Int'l Symp. on VLSI Technology, Systems, and Applications, Taipei, Taiwan, pp. 54-57, June 1999. (Invited Talk) .
  206. J. Cong, J. Fang and K.-Y. Khoo. Via Design Rule Consideration in Multi-Layer Maze Routing Algorithms. Proc. Intl Symposium on Physical Design, Monterey, California, pp. 214-220, April 1999.
  207. C.-C. Cang and J. Cong. Crosstalk Noise Control in Gridless General-Area Routing. ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), Monterey, California, pp. 117-122, March 8-9, 1999.
  208. J. Cong and David Z. Pan. Interconnect Delay and Area Estimation for Multiple-Pin Nets. ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), Monterey, California, pp. 179-184, March 8-9, 1999.
  209. J. Cong, C. Wu and E. Ding. Cut Ranking and Pruning: Enabling A General And Efficient FPGA Mapping Solution. Proc. ACM Intl. Symp. on FPGA, Monterey, California, pp. 29-35, February 1999.
  210. J. Cong and D. Z. Pan. Interconnect Delay Estimation Models for Synthesis and Design Planning. Proc. of ASP-DAC'99 Hong Kong, China, pp. 97-100, January 1999.
  211. J. Cong, T. Kong, D. Xu, F. Liang, J. S. Liu and W. H. Wong. Relaxed Simulated Tempering for VLSI Floorplan Designs. Proc. of ASP-DAC'99 Hong Kong, China, pp. 13-16, January 1999.
  212. J. Cong and S. K. Lim. Multiway Partitioning with Pairwise Movement. Proc. ACM/IEEE International Conference on Computer Aided Design, San Jose, California, pp. 512-516, November 1998.
  213. D. Kirovski, Y.-Y. Hwang, M. Potkonjak and J. Cong. Intellectual Property Protection by Watermarking Combinational Logic Synthesis Solutions. Proc. ACM/IEEE International Conference on Computer Aided Design, San Jose, California, pp. 194-198, November 1998.
  214. J. Cong and S. Xu. Delay-Oriented Technology Mapping for Heterogeneous FPGAs with Bounded Resources. Proc. ACM/IEEE International Conference on Computer Aided Design, San Jose, California, pp. 40-45, November 1998.
  215. J. Cong and S. Xu. Delay-Optimal Technology Mapping for FPGAs with Heterogeneous LUTs. Proc. of 35th Design Automation Conf., San Francisco, California, pp. 704-707, June 1998.
  216. J. Cong and Z. Pan. Interconnect Performance Estimation Models for Synthesis and Design Planning. ACM/IEEE Int'l Workshop on Logic Synthesis, pp. 427-433, June 1998.
  217. J. Cong and P. Madden. Performance Driven Multi-Layer General Area Routing for PCB/MCM Designs. Proc. of 35th Design Automation Conf., San Francisco, California, pp. 356-361, June 1998.
  218. J. Cong and C. Wu . Optimal FPGA Mapping and Retiming with Efficient Initial State Computation. Proc. of 35th Design Automation Conf., San Francisco, California, pp. 330-335, June 1998.
  219. J. Cong. Challenges and Opportunities for Design Innovations in Nanometer Technologies. Invited Semiconductor Research Corporation Design Sciences Concept Paper, pp. 1 - 15, January 1998. (Also appeared in the International Symposium on Computing and Microelectronics Technologies, May 1998).
  220. Cong, J. and L. He. An Efficient Technique for Device and Interconnect Optimization in Deep Submicron Designs. ACM Int'l Symposium on Physical Design, pp 45-51, April, 1998.
  221. J. Cong and S. Xu . Technology Mapping for FPGAs with Embedded Memory Blocks. Proc. ACM International Symposium on FPGA, Monterey, California, pp. 179-188, February 1998.
  222. J. Cong and Y. Hwang. Boolean Matching for Complex PLBs in LUT based FPGAs with Application to Architecture Evaluation. Proc. ACM International Symposium on FPGA, Monterey, California, pp. 27-34, February 1998.
  223. J. Cong, L. He, C. K. Koh and Z. Pan. Global Interconnect Sizing and Spacing with Consideration of Coupling Capacitance. Proc. IEEE Int'l Conf. on Computer-Aided Design, San Jose, California, pp. 628-633, November 1997.
  224. J. Cong, H. P. Li, S. K. Lim, T. Shibuya and D. Xu. Large Scale Circuit Partitioning with Loose/Stable Net Removal and Signal Flow Based Clustering. Proc. IEEE Int'l Conf. on Computer-Aided Design, San Jose, California, pp. 441-446, November 1997.
  225. J. Cong, L. He, K. Y. Khoo, C. K. Koh and Z. Pan. Interconnect Design for Deep Submicron ICs. Proc. IEEE Int'l Conf. on Computer-Aided Design, San Jose, California, pp. 478-485, November 1997. (Invited Embedded Tutorial) .
  226. J. Cong and C. K. Koh. Interconnect Layout Optimization Under Higher-Order RLC Model. Proc. IEEE Int'l Conf. on Computer-Aided Design, San Jose, California, pp. 713-720, November 1997.
  227. J. Cong and C. Wu. FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential Circuits. Proc. 34th ACM/IEEE Design Automation Conf., Anaheim, California, pp. 644-649, June 1997.
  228. J. Cong, L. He, A. B. Kahng, D. Noice, N. Shirali and S. H.-C. Yen. Analysis and Justification of a Simple, Practical 2 1/2-D Capacitance Extraction Methodology. Proc. 34th ACM/IEEE Design Automation Conf., Anaheim, California, pp. 627-632, June 1997.
  229. C.- C. Chang. and J. Cong. An Efficient Approach to Multi-layer Layer Assignment with Application to Via Minimization. Proc. 34th ACM/IEEE Design Automation Conf., Anaheim, California, pp. 600-603, June 1997.
  230. J. Cong and K.-S. Leung. Fast Optimal Algorithms for the Minimum Rectilinear Steiner Arborescence Problem. Proc. Intl Symposium on Circuits and Systems, pp. 1568-1571, May 1997.
  231. J. Cong, A. B. Kahng and K.-S. Leung. Efficient Heuristics for the Minimum Shortest Path Steiner Arborescence Problem with Applications to VLSI Physical Design. Proc. Intl Symposium on Physical Design, Napa, California, pp. 88-95, April 1997.
  232. J. Cong and Patrick H. Madden. Performance Driven Global Routing for Standard Cell Design. Proc. Intl Symposium on Physical Design, Napa, California, pp 73-80, April 1997.
  233. J. Cong and Y. Hwang. Partially-Dependent Functional Decomposition with Applications in FPGA Synthesis and Mapping. Proc. ACM/SIGDA Int'l Symp. on Field-Programmable Gate-Arrays, Monterey, California, pp. 35-42, February 1997.
  234. J. Cong. Modeling and Layout Optimization of VLSI Devices and Interconnects In Deep Submicron Design. Proc. Asia and South Pacific Design Automation Conf., Chiba, Japan, pp. 121-126, January 1997.
  235. J. Cong and L. He. An Efficient Approach to Simultaneous Transistor and Interconnect Sizing. Proc. IEEE Int'l Conf. on Computer-Aided Design, San Jose, California, pp. 181-186, November 1996.
  236. T. Okamoto and J. Cong. Buffered Steiner Tree Construction with Wire Sizing for Interconnect Layout Optimization. Proc. IEEE Int'l Conf. on Computer-Aided Design, San Jose, California, pp. 44-49, November 1996.
  237. J. Cong and C. Wu. An Improved Algorithm for Performance-Optimal Technology Mapping with Retiming in LUT-Based FPGA Design. Proc. IEEE Int'l Conf. on Computer Design, Austin, Texas, pp. 572-578, October 1996.
  238. J. Cong, C. K. Koh and K. S. Leung. Simultaneous Buffer and Wire Sizing for Performance and Power Optimization. Proc. IEEE Int'l Symp. on Low Power Electronics and Design., Monterey, California, pp 271-276, August 1996.
  239. J. Cong and Y. Y. Hwang. Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-based FPGA Design. Proc. 33rd ACM/IEEE Design Automation Conf., pp. 726-729, June 1996.
  240. J. Cong and L. He. Simultaneous Transistor and Interconnect Sizing Using General Dominance. Proc. 5th ACM/SIGDA Physical Design Workshop, Reston Virginia, pp. 34-39, April 1996.
  241. T. Okamoto and J. Cong. Interconnect Layout Optimization by Simultaneous Steiner Tree Construction and Buffer Insertion. Proc. 5th ACM/SIGDA Physical Design Workshop, Reston, Virginia, pp. 1-6, April 1996.
  242. J. Cong, J. Peck and Y. Ding. RASP: A General Logic Synthesis System for SRAM-based FPGAs. Proc. ACM/SIGDA Int'l Symp. on Field-Programmable Gate-Arrays, Monterey, California, pp. 137 - 143, February 1996.
  243. L. Kleinrock, M. Gerla, N. Bambos, J. Cong, E. Gafni, L. Bergman, J. Bannister, S. Monacos, T. Bujewski, P. C. Hu, B. Kannan, B. Kwan, E. Leonardi, J. Peck, P. Palnati, and S. Walton. The Supercomputer Supernet(SSN): A High-Speed Electro-Optic Campus and Metropolitan Network. Proc. SPIE, San Jose, California, vol. 2692, pp. 22-33, January 1996.
  244. J. Cong and Lei He. Optimal Wiresizing for Interconnects with Multiple Sources. Proc. ACM/IEEE Int'l Conf. on Computer-Aided Design, Santa Clara, California, pp. 568-574, November 1995. (Full version is available as UCLA Tech. Report 95-00031.).
  245. J. Cong, A. B. Kahng, C. K. Koh and C. W. Tsao. Bounded-Skew Clock and Steiner Routing. Proc. ACM/IEEE Int'l Conf. on Computer-Aided Design, Santa Clara, California, pp. 66-71, November 1995.
  246. J. Cong and D. Xu. Exploiting Signal Flow and Logic Dependency in Standard Cell Placement. Proc. Asia and South Pacific Design Automation Conf., Chiba, Japan, pp. 399-404, August 1995.
  247. J. Cong and C. K. Koh. Minimum-Cost Bounded-Skew Clock Routing. Proc. Int'l Symp. on Circuits and Systems, Seattle, Washington, pp. 215-218, May 1995.
  248. J. Cong and P. Madden. Performance Driven Routing with Multiple Sources. Proc. Int'l Symp. on Circuits and Systems, Seattle, Washington, pp. 203-206, May 1995.
  249. J. Cong and Y. Ding. On Nominal Delay Minimization in LUT-Based FPGA Technology Mapping. Proc. ACM/SIGDA Int'l Symp. on Field-Programmable Gate-Arrays, Monterey, California, pp. 82-88, February 1995.
  250. J. Cong and Y. Hwang. Simultaneous Depth and Area Minimization in LUT-Based FPGA Mapping. Proc. ACM/SIGDA Int'l Symp. on Field-Programmable Gate-Arrays, Monterey, California, pp. 68-74, February 1995.
  251. R. Bagrodia, Z. Li, V. Jha, Y. Chen and J. Cong. Parallel Logic Level Simulation of VLSI Circuits. Proc. IEEE Winter Simulation Conf., pp. 1354-1361, December 1994.
  252. J. Cong and C. K. Koh. Simultaneous Driver and Wire Sizing for Performance and Power Optimization. Proc. Int'l Conf. on Computer-Aided Design, pp. 206-212, November 1994.
  253. J. Cong, W. Labio and N. Shivakumar. Multi-Way VLSI Circuit Partitioning Based on Dual Net Representations. Proc. Int'l Conf. on Computer-Aided Design, pp. 56-62, November 1994.
  254. J. Cong, Z. Li and R. Bagrodia. Acyclic Multi-Way Partitioning of Boolean Networks. Proc. 31st IEEE/ACM Design Automation Conf., pp. 670-675, June 1994.
  255. J. Cong, C. K. Koh and K. S. Leung. Wiresizing with Driver Sizing for Performance and Power Optimization. Proc. Int'l Workshop on Low Power Design, pp. 81-86, April 1994.
  256. J. Cong and Y. Ding. Beyond The Combinatorial Limit in Depth Minimization For LUT-Based FPGA Designs. Proc. Int'l Conf. on Computer-Aided Design, pp. 634-639, November 1993.
  257. J. Cong and K. S. Leung. Optimal Wiresizing Under the Distributed Elmore Delay Model. Proc. Int'l Conf. on Computer-Aided Design, pp. 110-114, November 1993.
  258. T. Gao, K. C. Chen, J. Cong, Y. Ding and C. L. Liu. Placement and Placement Driven Technology Mapping for FPGA. Proc. IEEE ASIC Conf., pp. 91-94, September 1993.
  259. J. Cong and Y. Ding. An Optimal Performance-Driven Technology Mapping Algorithm For LUT-Based FPGAs Under Arbitrary Net-Delay Models. Proc. Int'l Conf. on Computer-Aided Design and Computer Graphics, pp. 599-604, August 1993.
  260. J. Cong and M. Smith. A Parallel Bottom-up Clustering Algorithm with Applications to Circuit Partitioning in VLSI Designs. Proc. ACM/IEEE 30th Design Automation Conference, pp. 755-760, June 1993.
  261. J. Cong, K. S. Leung and D. Zhou. Performance-Driven Interconnect Design Based on Distributed RC Delay Model. Proc. ACM/IEEE 30th Design Automation Conference, pp. 606-611, June 1993.
  262. K. Y. Khoo and J. Cong. An Efficient Multilayer MCM Router Based on Four-Via Routing. Proc. ACM/IEEE 30th Design Automation Conference, pp. 590-595, June 1993.
  263. J. Cong and Y. Ding. On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping. Proc. ACM/IEEE 30th Design Automation Conference, pp. 213-218, June 1993.
  264. C. J. Alpert, J. Cong, A. B. Kahng, G. Robins and M. Sarrafzadeh. Minimum Density Interconnection Trees. Proc. IEEE Int'l Symp. on Circuits and Systems, pp. 1865-1868, May 1993.
  265. S. Iman, M. Pedram, C. Fabian and J. Cong. Finding Uni-Directional Cuts Based on Physical Partitioning and Logic Restructuring. 4th ACM/SIGDA Physical Design Workshop, pp. 187-198, April 1993.
  266. D. Zhou, F. Tsui, J. Cong, and D. Gao. MCM Layout with Distributive RCL-Model . Proc. IEEE Multi-Chip Module Conf., pp. 191-197, March 1993.
  267. K. Y. Khoo and J. Cong. A Fast Four-Via Multilayer MCM Router. Proc. IEEE Multi-Chip Module Conf., pp. 179-184, March 1993.
  268. D. Boese, J. Cong, A. Kahng, K. S. Leung and D. Zhou. On High-Speed VLSI Interconnects: Analysis and Design. Proc. IEEE Asia-Pacific Conference on Circuits and Systems, pp. 35-40, December 1992. (Invited paper) .
  269. J. Cong and Y. Ding. An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs. Proc. IEEE Int'l Conference on Computer-Aided Design, pp. 48-53, November 1992. (Highlighted paper).
  270. J. Cong, Y. Ding, A. Kahng, P. Trajmar and K. C. Chen. An Improved Graph-Based FPGA Technology Mapping Algorithm For Delay Optimization. Proc. IEEE Int'l Conference on Computer Designs, pp. 154-158, October 1992.
  271. K. C. Chen and J. Cong. Maximal Reduction of Lookup-Table Based FPGAs. Proc. European Design Automation Conference, pp. 224-229, September 1992.
  272. K. Y. Khoo and J. Cong. A Fast Multilayer General Area Router for MCM Designs. Proc. European Design Automation Conference, pp. 292-297, September 1992.
  273. J. Cong, L. Hagen, and A. Kahng. Net Partitions Yield Better Module Partitions. Proc. ACM/IEEE 29th Design Automation Conference, pp. 47-52, June 1992. (Best Paper Award Candidate).
  274. J. Cong, A. Kahng, G. Robins, M. Sarrafzadeh, and C. K. Wong. Provably Good Algorithms Performance-Driven Global Routing. Proc. IEEE International Symposium on Circuits and Systems, pp. 2240-2243, May 1992.
  275. J. Cong, A. Kahng, P. Trajmar and K. C. Chen. DAG-Map:Graph Based FPGA Technology Mapping for Delay Optimization. Proc. ACM Int'l Workshop on Field Programmable Gate Arrays, pp. 77-82, February 1992.
  276. J. Cong and K. Khoo. A Provable Near-Optimal Algorithm for the Channel Pin Assignment Problem. Proc. IEEE Int'l Conference on Computer Design, pp. 319-322, October 1991.
  277. J. Cong, A. Kahng and G. Robins. Performance-Driven Global Routing for Cell Based ICs. Proc. IEEE Int'l Conference on Computer Design, pp. 170-173, October 1991.
  278. J. Cong, L. Hagen and A. Kahng. Random Walks for Circuit Clustering. Proc. IEEE 4th Int'l ASIC Conf., pp. 14-2.1 - 14-2.4, September 1991.
  279. J. Cong, A. Kahng and G. Robins. On Clock Routing for General Cell Layouts. Proc. IEEE 4th Int'l ASIC Conf., pp. 14-5.1 - 14-5.4, September 1991.
  280. A. Kahng, J. Cong and G. Robins. High-Performance Clock Routing Based on Recursive Geometric Matching. Proc. ACM/IEEE 28th Design Automation Conf., pp. 322-327, June 1991.
  281. J. Cong, B. Preas and C. L. Liu. General Models and Algorithms for Over-the-Cell Routing in Standard Cell Design. Proc. 27th ACM/IEEE Design Automation Conf., pp. 709-715, June 1990.
  282. J. Cong and C. L. Liu. On the k-Layer Planar Subset and Via Minimization Problems. Proc. of European Design Automation Conf., pp. 459-463, March 1990.
  283. S. Dong, J. Cong and C. L. Liu. Constrained Floorplan Design for Flexible Blocks. Proc. Int'l Conf. on Computer-Aided Design, pp. 488-491, November 1989.
  284. J. Cong. Pin Assignment with Global Routing for General Cell Designs. Proc. Int'l Conf. on Computer-Aided Design, pp. 302-305, November 1989.
  285. N. Hasan, J. Cong and C. L. Liu. An Integer Linear Programming Approach to General Fault Covering Problems. Proc. Int'l Workshop on Defect and Fault Tolerance in VLSI Systems, pp. 146-156, October 1989.
  286. K. S. The, D. F. Wong and J. Cong. VIA Minimization by Layout Modification. Proc. 26th ACM/IEEE Design Automation Conf., pp. 799-802, June 1989.
  287. N. Hasan, J. Cong and C. L. Liu. A New Formulation of Yield Enhancement Problems for Reconfigurable Chips. Proc. Int'l Conf. Computer-Aided Design, pp. 520-523, November 1988.
  288. J. Cong and B. Preas. A New Algorithm for Standard Cell Global Routing. Proc. Int'l Conf. on Computer-Aided Design," pp 176-179, November 1988. (Highlighted paper).
  289. J. Cong and C. L. Liu. Over-the-Cell Channel Routing. Proc. Int'l Conf. Computer-Aided Design," pp. 80-83, November 1988.
  290. N. Hasan, J. Cong and C. L. Liu. A General Model for Fault Covering Problems in Reconfigurable Arrays. Proc. Int'l Workshop on Defect and Fault Tolerance in VLSI Systems, pp. 319-326, 1988.
  291. J. Cong and D. F. Wong. How to Obtain More Compactable Channel Routing Solutions. Proc. 25th IEEE/ACM Design Automation Conf., pp 663-666, June 1988.
  292. J. Cong, D. F. Wong and C. L. Liu. A New Approach to the Three Layer Channel Routing. Proc. Int'l Conf. Computer-Aided Design, pp. 378-381, November 1987.