VAST lab at UCLA

The VAST lab at UCLA investigates cutting-edge research topics at the intersection of VLSI technologies, design automation,  architecture and compiler optimization at multiple scales, from micro-architecture building blocks,  to heterogeneous compute nodes, and scalable data centers.  Current focuses include architecture and design automation for emerging technologies, customizable domain-specific computing with applications to multiple domains, such as imaging processing, bioinformatics, data mining and machine learning.

Latest News

May 8, 2015 | 0 comments

A research paper by Jason Cong, a Chancellor’s Professor in UCLA’s Computer Science Department, and his former doctoral student, Yan Zhang, was selected as the 10-Year Retrospective...

January 23, 2015 | 0 comments

The paper entitled “Thermal-Driven Multilevel Routing for 3-D ICs,” co-authored by Prof. Jason Cong and his former PhD student Dr. Yan Zhang is selected as the 10-Year Retrospective Most Influential Paper in the 2015 Asia South-Pacific Design...

November 10, 2014 | 0 comments

Congratulations to Jason Cong and coauthors Jie Wei and Yan Zhang.  Their 2004 paper, A Thermal-Driven Floorplanning Algorithm for 3D ICs, has received this year's ICCAD Ten-Year Retrospective Most Influential Paper Award. ICCAD (International...

Latest Publications

[PDF]: CMOST: A System-Level FPGA Compilation Framework
Conference publication
Peng Zhang, Muhuan Huang, Bingjun Xiao, Hui Huang, and Jason Cong
[PDF]: On-chip Interconnection Network for Accelerator-Rich Architectures
Conference publication
Jason Cong, Michael Gill, Yuchen Hao, Glenn Reinman, and Bo Yuan
[PDF]: A Novel High-Throughput Acceleration Engine for Read Alignment
Conference publication
Yu-Ting Chen, Jason Cong, Jie Lei, and Peng Wei
[PDF]: ARACompiler: A Prototyping Flow and Evaluation Framework for Accelerator-Rich Architectures
Conference publication
Yu-Ting Chen, Jason Cong, and Bingjun Xiao
Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks
Conference publication
Chen Zhang, Peng Li, Guangyu Sun, Yijin Guan, Bingjun Xiao, Jason Cong
[PDF]: Resource-Aware Throughput Optimization for High-Level Synthesis
Conference publication
Peng Li, Peng Zhang, Louis-Noël Pouchet, Jason Cong
[PDF]: High Efficiency VLSI Implementation of an Edge-directed Video Up-scaler Using High Level Synthesis
Conference publication
M. Li, P. Zhang, C. Zhu, H. Jia, X. Xie, J. Cong, and W. Gao
[PDF]: Minimizing Computation in Convolutional Neural Networks
Conference publication
Jason Cong and Bingjun Xiao
[PDF]: A Scalable, High-Performance Customized Priority Queue
Conference publication
Muhuan Huang, Kevin Lim and Jason Cong

Our Projects

Single event upsets (SEUs) are a source of concern for correct operation of CMOS circuits. The severity of the problem is increased as the transistor size and supply voltage decrease. In the traditional or numerical notion of correctness, every output has to be correct to the last bit. However...

Reconfigurable computing combines the flexibility of software along with the high performance of hardware and exhibits many advantages including flexibility, reduced time-to-market, lower system costs, and capability of adding new features. However, there are a number of drawbacks associated...

In this paper we introduce a novel FPGA architecture with RRAM-based programmable interconnects (FPGA-RPI). Programmable interconnects are the dominant part of FPGA. We use RRAMs to build programmable interconnects, and we optimize their structures by exploiting opportunities that emerge in...

With the increasing of the system complexity, the needs of system level design automation becomes more and more urgent. The maturity of high-level synthesis pushes the desgin abstraction from register-transfer level (RTL) to software programming language like C/C++. However, the state-of-art...

http://www.cdsc.ucla.edu

To meet ever-increasing computing needs and overcome power density limitations, the computing industry has entered theera of parallelization, with tens to hundreds of computing cores integrated into a single...

Software Releases

CMOST is a system-level design automation framework for FPGA. The main features are:

  • Analyze and extract...

PolyOpt/HLS is a polyhedral loop optimization framework dedicated to data reuse optimization for High-Level Synthesis, integrated in the ROSE compiler. The main features are:

  • Automatic extraction of regions that can be optimized in the polyhedral model
  • Full support of PoCC...

The xPilot Team:

  • Professor Jason Cong
  • Researchers: Deming Chen, Yiping Fan, Guoling Han, Wei Jiang, Bin Liu, Junjuan Xu, Zhiru Zhang

...