VAST lab at UCLA

The VAST lab at UCLA investigates cutting-edge research topics at the intersection of VLSI technologies, design automation,  architecture and compiler optimization at multiple scales, from micro-architecture building blocks,  to heterogeneous compute nodes, and scalable data centers.  Current focuses include architecture and design automation for emerging technologies, customizable domain-specific computing with applications to multiple domains, such as imaging processing, bioinformatics, data mining and machine learning.

Latest News

October 6, 2017 | 0 comments

Prof. Cong delivered a keynote speech at the 2017 IEEE International Symposium on Workload Characterization (IISWC'17) on October 2, 2017 held in Seattle, WA. The title of Prof. Cong's speech is "Characterization and...

October 6, 2017 | 0 comments

Computer Science Department authors Jason Cong, Zhenman Fang, Michael Gill, Farnoosh Javadi, and Glenn Reinman have received a Best Paper Award at MEMSYS 2017 (2-5 October, Washington DC) for their recent paper AIM: Accelerating...

September 29, 2017 | 0 comments

This collaborative work involves a team of researchers from several areas of UCLA.  Professor Jason Cong and Professor Tad Blair from UCLA’s Brain Research Institute are refining the wireless miniscope to give it built-in, energy-efficient...

Latest Publications

[PDF]: Impulse response analysis of carrier-modulated multiband RF-interconnect (MRFI)
Journal publication
Yanghyo Kim, Wei-Han Cho, Yuan Du, Jason Cong, Tatsuo Itoh, and Mau-Chung Frank Chang
[PDF]: HLScope+: Fast and Accurate Performance Estimation for FPGA HLS
Conference publication
Y. Choi, P. Zhang, P. Li, and J. Cong
AIM: Accelerating Computational Genomics through Scalable and Noninvasive Accelerator-Interposed Memory
Conference publication
Jason Cong, Zhenman Fang, Farnoosh Javadi, and Glenn Reinman
Bandwidth Optimization Through On-Chip Buffer Restructuring for HLS
Conference publication
Jason Cong, Peng Wei, Cody Hao Yu, and Peipei Zhou
Automated Systolic Array Architecture Synthesis for High Throughput CNN Inference on FPGAs
Conference publication
Xuechao Wei, Cody Hao Yu, Peng Zhang, Youxiang Chen, Yuxin Wang, Han Hu, Yun Liang, and Jason Cong
[PDF]: A 125 GHz Transceiver in 65 nm CMOS Assembled With FR4 PCB Antenna for Contactless Wave-Connectors
Conference publication
Yanghyo Kim, Yuan Du, Adrian Tang, Yan Zhao, Brian Lee, Huan-Neng Chen, Chewnpu Jou, Jason Cong, Tatsuo Itoh, and Mau-Chung Frank Chang
[PDF]: FP-DNN: An Automated Framework for Mapping Deep Neural Networks onto FPGAs with RTL-HLS Hybrid Templates
Conference publication
Yijin Guan, Hao Liang, Ningyi Xu, Wenqiang Wang, Shaoshuai Shi, Xi Chen, Guangyu Sun, Wei Zhang, and Jason Cong
[PDF]: HLScope: High-Level Performance Debugging for FPGA Designs
Conference publication
Young-kyu Choi and Jason Cong
[PDF]: Supporting Address Translation for Accelerator-Centric Architectures
Conference publication
Jason Cong, Zhenman Fang, Yuchen Hao, and Glenn Reinman

Our Projects

Many applications in precision medicine present significant computational challenges.  For example, the computation demand for personalized cancer treatment is prohibitively high for the general-purpose computing technologies, as tumor heterogeneity requires great sequencing depths, structural...

With the increasing of the system complexity, the needs of system level design automation becomes more and more urgent. The maturity of high-level synthesis pushes the desgin abstraction from register-transfer level (RTL) to software programming language like C/C++. However, the state-of-art...

To meet ever-increasing computing needs and overcome power density limitations, the computing industry has entered theera of parallelization, with tens to hundreds of computing cores integrated into a single...

Software Releases

Cloud-scale BWAMEM (CS-BWAMEM) is an ultrafast and highly scalable aligner built on top of cloud infrastructures, including Spark and Hadoop distributed file system (HDFS). It leverages the abundant computing resources in a public or private cloud to fully exploit the parallelism obtained from...

With the rapid evolution of CPU-FPGA heterogeneous acceleration platforms, it is critical for both platform developers and users to quantify the fundamental microarchitectural features of the platforms. We developed a set of microbenchmarks to evaluate mainstream CPU-FPGA platforms.


PARADE is a cycle-accurate full-system simulation platform that enables the design and exploration of the emerging accelerator-rich architectures (ARA). It extends the widely used gem5 simulator with high-level synthesis (HLS) support.