VAST lab at UCLA

The VAST lab at UCLA investigates cutting-edge research topics at the intersection of VLSI technologies, design automation,  architecture and compiler optimization at multiple scales, from micro-architecture building blocks,  to heterogeneous compute nodes, and scalable data centers.  Current focuses include architecture and design automation for emerging technologies, customizable domain-specific computing with applications to multiple domains, such as imaging processing, bioinformatics, data mining and machine learning.

Latest News

August 9, 2016 | 0 comments

Prof. Jason Cong delivered the opening keynote speech at the The 11th IEEE International Conference on Networking, Architecture, and Storage (NAS 2016) on August 8, 2016 held at Long Beach, California.  NAS provides a high-...

June 28, 2016 | 0 comments

Congratulations to new PhD, Dr. Yu-Ting Chen under supervision of Prof. Jason Cong! His thesis is "...

June 13, 2016 | 0 comments

Dr. Jason Cong, a Chancellor’s Professor at the Computer Science Department, with joint appointment from Electrical Engineering Department of University of California, Los Angeles, has been selected to receive the 2016 Technical Achievement...

Latest Publications

FCUDA-Bus: Hierarchical and Scalable BusArchitecture Generation on FPGAs with High-Level Synthesis
Journal publication
Y. Chen, T. Nguyen, Y. Chen, S.T. Gurumani, Y. Liang, K. Rupnow, J. Cong, W.-M. Hwu, D. Chen
Caffeine: Towards Uniformed Representation and Acceleration for Deep Convolutional Neural Networks
Conference publication
Chen Zhang, Zhenman Fang, Peipei Zhou, Peichen Pan, Jason Cong
Energy-Efficient CNN Implementation on a Deeply Pipelined FPGA Cluster
Conference publication
Chen Zhang, Di Wu, Jiayu Sun, Guangyu Sun, Guojie Luo and Jason Cong
[PDF]: When Apache Spark Meets FPGAs: A Case Study for Next-Generation DNA Sequencing Acceleration
Conference publication
Yu-Ting Chen, Jason Cong, Zhenman Fang, Jie Lei and Peng Wei
Heterogeneous Datacenters: Options and Opportunities
Conference publication
Jason Cong, Muhuan Huang, Di Wu, and Cody Hao Yu
A Quantitative Analysis on Microarchitectures of Modern CPU-FPGA Platforms
Conference publication
Young-kyu Choi, Jason Cong, Zhenman Fang, Yuchen Hao, Glenn Reinman, and Peng Wei
Source-to-Source Optimization for HLS
Book chapter
J. Cong, M. Huang, P. Pan, Y. Wang, P. Zhang
[PDF]: Energy Efficiency of Full Pipelining: A Case Study for Matrix Multiplication
Conference publication
Peipei Zhou, Hyunseok Park, Zhenman Fang, Jason Cong, Andre DeHon
The SMEM Seeding Algorithm Acceleration for DNA Sequence Alignment
Conference publication
Mau-Chung Frank Chang, Yu-Ting Chen, Jason Cong, Po-Tsang Huang, Chun-Liang Kuo and Cody Hao Yu
Scaling Up Physical Design: Challenges and Opportunities
Conference publication
Guojie Luo, Wentai Zhang, Jiaxi Zhang, and Jason Cong

Our Projects

NSF and Intel support the development of domain-specific hardware to address health care needs.

In partnership with Intel Corporation, NSF announced the first InTrans award of $3 million to a team of researchers who are designing customizable, domain-specific computing technologies for...

With the increasing of the system complexity, the needs of system level design automation becomes more and more urgent. The maturity of high-level synthesis pushes the desgin abstraction from register-transfer level (RTL) to software programming language like C/C++. However, the state-of-art...

To meet ever-increasing computing needs and overcome power density limitations, the computing industry has entered theera of parallelization, with tens to hundreds of computing cores integrated into a single...

Software Releases

Cloud-scale BWAMEM (CS-BWAMEM) is an ultrafast and highly scalable aligner built on top of cloud infrastructures, including Spark and Hadoop distributed file system (HDFS). It leverages the abundant computing resources in a public or private cloud to fully exploit the parallelism obtained from...

With the rapid evolution of CPU-FPGA heterogeneous acceleration platforms, it is critical for both platform developers and users to quantify the fundamental microarchitectural features of the platforms. We developed a set of microbenchmarks to evaluate mainstream CPU-FPGA platforms.


PARADE is a cycle-accurate full-system simulation platform that enables the design and exploration of the emerging accelerator-rich architectures (ARA). It extends the widely used gem5 simulator with high-level synthesis (HLS) support.