VAST lab at UCLA

The VAST lab at UCLA investigates cutting-edge research topics at the intersection of VLSI technologies, design automation,  architecture and compiler optimization at multiple scales, from micro-architecture building blocks,  to heterogeneous compute nodes, and scalable data centers.  Current focuses include architecture and design automation for emerging technologies, customizable domain-specific computing with applications to multiple domains, such as imaging processing, bioinformatics, data mining and machine learning.

Latest News

January 28, 2016 | 0 comments

Prof. Jason Cong delivered a keynote speech on "Compilation for Customized Computing -- From Single-Chips to Data Centers” at the 21st Asia and South Pacific Design Automation Conference
(ASP-DAC 2016) in Macao, China on Jan. 28, 2016.   ...

November 16, 2015 | 0 comments

Prof Cong gave keynote speech "Datacenter-Scale Customizable Computing" at first International Workshop on Heterogeneous High-performance Reconfigurable Computing...

November 8, 2015 | 0 comments

Prof. Cong gave keynote speech entitled "Machine Learning on FPGAs" at HALO’2015 (the First Workshop on Hardware and Algorithms for Learning On-a-Chip) co-located at the...

Latest Publications

Acceleration of EM-Based 3D CT Reconstruction Using FPGA
Journal publication
Young-kyu Choi and Jason Cong
[PDF]: Impact of Loop Transformations on Software Reliability
Conference publication
Jason Cong, and Cody Hao Yu
[PDF]: PARADE: A Cycle-Accurate Full System Simulation Platform for Accelerator-Rich Architectural Design and Exploration
Conference publication
Jason Cong, Zhenman Fang, Michael Gill, and Glenn Reinman
[PDF]: CS-BWAMEM: A fast and scalable read aligner at the cloud scale for whole genome sequencing
Conference publication
Yu-Ting Chen, Jason Cong, Sen Li, Myron Peto, Paul Spellman, Peng Wei, and Peipei Zhou
[PDF]: InterFS: An Interplanted Distributed File System to Improve Storage Utilization
Conference publication
Peng Wang, Le Cao, Chunbo Lai, Leqi Zou, Guangyu Sun, and Jason Cong
Customizable Computing - Synthesis Lectures on Computer Architecture
Y-T. Chen, J. Cong, M. Gill, G. Reinman, and B. Xiao
[PDF]: CMOST: A System-Level FPGA Compilation Framework
Conference publication
Peng Zhang, Muhuan Huang, Bingjun Xiao, Hui Huang, and Jason Cong
[PDF]: On-chip Interconnection Network for Accelerator-Rich Architectures
Conference publication
Jason Cong, Michael Gill, Yuchen Hao, Glenn Reinman, and Bo Yuan
[PDF]: A Novel High-Throughput Acceleration Engine for Read Alignment
Conference publication
Yu-Ting Chen, Jason Cong, Jie Lei, and Peng Wei

Our Projects

Single event upsets (SEUs) are a source of concern for correct operation of CMOS circuits. The severity of the problem is increased as the transistor size and supply voltage decrease. In the traditional or numerical notion of correctness, every output has to be correct to the last bit. However...

Reconfigurable computing combines the flexibility of software along with the high performance of hardware and exhibits many advantages including flexibility, reduced time-to-market, lower system costs, and capability of adding new features. However, there are a number of drawbacks associated...

In this paper we introduce a novel FPGA architecture with RRAM-based programmable interconnects (FPGA-RPI). Programmable interconnects are the dominant part of FPGA. We use RRAMs to build programmable interconnects, and we optimize their structures by exploiting opportunities that emerge in...

With the increasing of the system complexity, the needs of system level design automation becomes more and more urgent. The maturity of high-level synthesis pushes the desgin abstraction from register-transfer level (RTL) to software programming language like C/C++. However, the state-of-art...

To meet ever-increasing computing needs and overcome power density limitations, the computing industry has entered theera of parallelization, with tens to hundreds of computing cores integrated into a single...

Software Releases

PARADE is a cycle-accurate full-system simulation platform that enables the design and exploration of the emerging accelerator-rich architectures (ARA). It extends the widely used gem5 simulator with high-level synthesis (HLS) support. 


CMOST is a system-level design automation framework for FPGA. The main features are:

  • Analyze and extract...

PolyOpt/HLS is a polyhedral loop optimization framework dedicated to data reuse optimization for High-Level Synthesis, integrated in the ROSE compiler. The main features are:

  • Automatic extraction of regions that can be optimized in the polyhedral model
  • Full support of PoCC...