VAST lab at UCLA

The VAST lab at UCLA investigates cutting-edge research topics at the intersection of VLSI technologies, design automation,  architecture and compiler optimization at multiple scales, from micro-architecture building blocks,  to heterogeneous compute nodes, and scalable data centers.  Current focuses include architecture and design automation for emerging technologies, customizable domain-specific computing with applications to multiple domains, such as imaging processing, bioinformatics, data mining and machine learning.

Latest News

November 23, 2016 | 0 comments

Prof. Cong delivered a keynote speech at the Symposium on Emerging Trends in Computing on Oct. 10, 2016 in Montreux, Switzerland. The title of Prof. Cong's speech is "Customizable Computing: Options and Opportunities”.  The objective of this...

November 21, 2016 | 0 comments

Prof. Jason Cong delivered a keynote speech at the The 11th Conference on Advanced Computer Architecture (ACA '2016...

August 9, 2016 | 0 comments

Prof. Jason Cong delivered the opening keynote speech at the The 11th IEEE International Conference on Networking, Architecture, and Storage (NAS 2016) on August 8, 2016 held at Long Beach, California.  NAS provides a high-...

Latest Publications

[PDF]: Throughput Optimization for Streaming Applications on CPU-FPGA Heterogeneous Systems
Conference publication
X. Wei, Y. Liang, T. Wang, S. Lu, and J. Cong
[PDF]: FPGA-based Accelerator for Long Short-Term Memory Recurrent Neural Networks
Conference publication
Y. Guan, Z. Yuan, G. Sun, and J. Cong
[PDF]: Platform Choices and Design Demands for IoT Platforms: Cost, Power, and Performance Tradeoffs
Journal publication
D. Chen, J. Cong, S. Gurumani, W.-m. Hwu, K. Rupnow, and Z. Zhang
Re-form: FPGA-powered true codesign flow for high-performance computing in the post-Moore era
Conference publication
Franck Cappello, Kazutomo Yoshii, Hal Finkel, and Jason Cong
Caffeine: Towards Uniformed Representation and Acceleration for Deep Convolutional Neural Networks
Conference publication
Chen Zhang, Zhenman Fang, Peipei Zhou, Peichen Pan, Jason Cong
Programming and Runtime Support to Blaze FPGA Accelerator Deployment at Datacenter Scale
Conference publication
Muhuan Huang, Di Wu, Cody Hao Yu, Zhenman Fang, Matteo Interlandi, Tyson Condie, and Jason Cong
FCUDA-Bus: Hierarchical and Scalable BusArchitecture Generation on FPGAs with High-Level Synthesis
Journal publication
Y. Chen, T. Nguyen, Y. Chen, S.T. Gurumani, Y. Liang, K. Rupnow, J. Cong, W.-M. Hwu, D. Chen
Energy-Efficient CNN Implementation on a Deeply Pipelined FPGA Cluster
Conference publication
Chen Zhang, Di Wu, Jiayu Sun, Guangyu Sun, Guojie Luo and Jason Cong
[PDF]: When Apache Spark Meets FPGAs: A Case Study for Next-Generation DNA Sequencing Acceleration
Conference publication
Yu-Ting Chen, Jason Cong, Zhenman Fang, Jie Lei and Peng Wei
Heterogeneous Datacenters: Options and Opportunities
Conference publication
Jason Cong, Muhuan Huang, Di Wu, and Cody Hao Yu

Our Projects

Many applications in precision medicine present significant computational challenges.  For example, the computation demand for personalized cancer treatment is prohibitively high for the general-purpose computing technologies, as tumor heterogeneity requires great sequencing depths, structural...

With the increasing of the system complexity, the needs of system level design automation becomes more and more urgent. The maturity of high-level synthesis pushes the desgin abstraction from register-transfer level (RTL) to software programming language like C/C++. However, the state-of-art...

To meet ever-increasing computing needs and overcome power density limitations, the computing industry has entered theera of parallelization, with tens to hundreds of computing cores integrated into a single...

Software Releases

Cloud-scale BWAMEM (CS-BWAMEM) is an ultrafast and highly scalable aligner built on top of cloud infrastructures, including Spark and Hadoop distributed file system (HDFS). It leverages the abundant computing resources in a public or private cloud to fully exploit the parallelism obtained from...

With the rapid evolution of CPU-FPGA heterogeneous acceleration platforms, it is critical for both platform developers and users to quantify the fundamental microarchitectural features of the platforms. We developed a set of microbenchmarks to evaluate mainstream CPU-FPGA platforms.


PARADE is a cycle-accurate full-system simulation platform that enables the design and exploration of the emerging accelerator-rich architectures (ARA). It extends the widely used gem5 simulator with high-level synthesis (HLS) support.