VAST lab at UCLA

The VAST lab at UCLA investigates cutting-edge research topics at the intersection of VLSI technologies, design automation,  architecture and compiler optimization at multiple scales, from micro-architecture building blocks,  to heterogeneous compute nodes, and scalable data centers.  Current focuses include architecture and design automation for emerging technologies, customizable domain-specific computing with applications to multiple domains, such as imaging processing, bioinformatics, data mining and machine learning.

Latest News

October 7, 2014 | 0 comments

Prof. Jason Cong is giving the keynote speech entitled "Design Automation Beyond High-Level Synthesis" at the 22nd IPIP/IEEE VLSI-SoC 2014 on Oct. 6, 2014.

VLSI-SoC 2014 is the 22nd in a series of international conferences sponsored by...

August 13, 2014 | 0 comments

In 14th IEEE International Symposium on Low Power Electronics and Design (ISLPED) 2014, La Jolla, CA, Professor Cong gave a keynote speech entitled...

July 27, 2014 | 0 comments

Congratulations to David Pan for  the appointment "Engineering Foundation Professor” at UT Austin. Last year David got Earl N. and Margaret Brasfield Endowed Faculty Fellowship in...

Latest Publications

[PDF]: Minimizing Computation in Convolutional Neural Networks
Conference publication
Jason Cong and Bingjun Xiao
[PDF]: A Scalable, High-Performance Customized Priority Queue
Conference publication
Muhuan Huang, Kevin Lim and Jason Cong
[PDF]: An Efficient and Flexible Host-FPGA PCIe Communication Library
Conference publication
Jian Gong, Tao Wang, Jiahua Chen, Haoyang Wu, Fan Ye, Songwu Lu and Jason Cong
[PDF]: System Light-Loading Technology for mHealth: Manifold-Learning-Based Medical Data Cleansing and Clinical Trials in WE-CARE Project
Journal publication
Anpeng Huang, Wenyao Xu, Zhinan Li, Linzhen Xie, Majid Sarrafzadeh, Xiaoming Li, and Jason Cong
[PDF]: Better-Than-Worst-Case Design: Progress and Opportunities
Journal publication
Jason Cong, Henry Duwe, Rakesh Kumar, and Sen Li
Accelerator-Rich Architectures: Opportunities and Progresses
Conference publication
Jason Cong, Mohammad Ali Ghodrat, Michael Gill, Beayna Grigorian, Karthik Gururaj, Glenn Reinman
[PDF]: GRT: A Reconfigurable SDR Platform with High Performance and Usability
Conference publication
T. Wang, G. Sun, J. Chen, J. Gong, H. Wu, X. Li, S. Lu and J. Cong
Architecture Support for Domain-Specific Accelerator-Rich CMPs
Journal publication
J. Cong, M. A. Ghodrat, M. Gill, B. Grigorian, G. Reinman
[PDF]: High-Speed mm-Wave Data-Link Based on Hollow Plastic Cable and CMOS Transceiver
Journal publication
Y. Kim, L. Nan, J. Cong, M-C.F. Chang

Our Projects

Single event upsets (SEUs) are a source of concern for correct operation of CMOS circuits. The severity of the problem is increased as the transistor size and supply voltage decrease. In the traditional or numerical notion of correctness, every output has to be correct to the last bit. However...

Reconfigurable computing combines the flexibility of software along with the high performance of hardware and exhibits many advantages including flexibility, reduced time-to-market, lower system costs, and capability of adding new features. However, there are a number of drawbacks associated...

In this paper we introduce a novel FPGA architecture with RRAM-based programmable interconnects (FPGA-RPI). Programmable interconnects are the dominant part of FPGA. We use RRAMs to build programmable interconnects, and we optimize their structures by exploiting opportunities that emerge in...

With the increasing of the system complexity, the needs of system level design automation becomes more and more urgent. The maturity of high-level synthesis pushes the desgin abstraction from register-transfer level (RTL) to software programming language like C/C++. However, the state-of-art...

To meet ever-increasing computing needs and overcome power density limitations, the computing industry has entered theera of parallelization, with tens to hundreds of computing cores integrated into a single...

Software Releases

CMOST is a system-level design automation framework for FPGA. The main features are:

  • Analyze and extract...

PolyOpt/HLS is a polyhedral loop optimization framework dedicated to data reuse optimization for High-Level Synthesis, integrated in the ROSE compiler. The main features are:

  • Automatic extraction of regions that can be optimized in the polyhedral model
  • Full support of PoCC...

The xPilot Team:

  • Professor Jason Cong
  • Researchers: Deming Chen, Yiping Fan, Guoling Han, Wei Jiang, Bin Liu, Junjuan Xu, Zhiru Zhang