Jason Cong

Volgenau Chair for Engineering Excellence

Director, Center for Customizable Domain-Specific Computing
Director, VLSI Architecture, Synthesis, and Technology (VAST) Laboratory  (former VLSI CAD Laboratory)

JASON CONG received his B.S. degree in computer science from Peking University in 1985, his M.S. and Ph. D. degrees in computer science from the University of Illinois at Urbana-Champaign in 1987 and 1990, respectively. Currently, he is the Volgenau Chair for Engineering Excellence in the UCLA Computer Science Department (with joint appointment in the Department of Electrical and Computer Engineering), the Director of Center for Domain-Specific Computing (funded by NSF Expeditions in Computing Award), and the director of VLSI Architecture, Synthesis, and Technology (VAST) Laboratory. He served as the chair of the UCLA Computer Science Department from 2005 to 2008.

Dr. Cong’s research interests include electronic design automation, customized computing for machine learning and big-data applications, quantum computing, and highly scalable algorithms. He has published over 500 research papers in these areas, including 16 Best Paper Awards (IEEE T-CAD’95, IPSD’05, HPCA'08, SASP'09, FCCM'11, FPGA’13, ISSS+CODES’13, ACM TODAES 2005, 2012, and 2013, MEMSYS'17,  ISLPED'18, FPGA'19, T-CAD'19, ICCAD'19, and FPGA'21). He also received three 10-Year Retrospective Most Influential Paper Award at ICCAD'14, ASPDAC'15, and ASPDAC'17, respectively.  His work on FPGA technology mapping (FlowMap) received the 2011 ACM/IEEE A. Richard Newton Technical Impact Award in Electric Design Automation “for pioneering work on technology mapping for FPGA that has made significant impact to the FPGA research community and industry”, and was the first inducted to the FPGA and Reconfigurable Computing Hall of Fame by ACM TCFPGA.  He was elected to an IEEE Fellow in 2000 for "for seminal contributions in computer-aided design of integrated circuits, especially in physical design automation, interconnect optimization, and synthesis of FPGAs", and ACM Fellow in 2008 "for contributions to electronic design automation".   He received the 2010 IEEE Circuits and System (CAS) Society Technical Achievement Award "For seminal contributions to electronic design automation, especially in FPGA synthesis, VLSI interconnect optimization, and physical design automation" and the 2016 IEEE Computer Society Technical Achievement Award “For setting the algorithmic foundations for high-level synthesis of field programmable gate arrays”.   Dr. Cong was elected as a member of the National Academy of Engineering in 2017 “for pioneering contributions to application-specific programmable logic via innovations in field programmable gate array (FPGA) synthesis”, and a Fellow of the National Academy of Inventors in 2020.  He received the University Research Award from the Semiconductor Industry Association (SIA) and the Semiconductor Research Corporation (SRC) for "research efforts to advance US semiconductor technology" in 2019.

In 2009, Dr. Cong led a group of twelve faculty members from UCLA, Rice, Ohio-State, and UC Santa Barbara and won an highly competitive NSF Expeditions in Computing Award (for $10M over five years). This award led to the establishment of the Center for Domain-Specific Computing (CDSC), which looks beyond parallelization and focuses on domain-specific customization to achieve drastic power-performance efficiency improvement. In 2014, Dr. Cong led the team won the very first award under the NSF Innovation Transition (InTrans) Program with additional $3M funding led by the Intel Corporation with matching support from NSF. This award supports the CDSC team to apply domain-specific computing to multiple critical applications in the health care domain.

Dr. Cong’s research publications have close to 30,000 citations according to Google Scholar with an H-index of 90 as of April 2021.  He is a frequent keynote speaker in major conferences in his fields, such as the IEEE Conference on Field-Programmable Technology (FPT'2005 and again in FPT'2014), the International Conference on Field Programmable Logic and Applications (FPL'2009), the IEEE Symposium on Application Specific Processors (SASP'2010), the IEEE International Conference on Application-Specific Systems (ASAP'2011), the Workshop on Synthesis and System Integration of Mixed Information technologies (2012), the Workshop on the Intersections of Computer Architecture and Reconfigurable Logic (2012), Intel Design and Test Technology Conference (DTTC'2012), the IEEE International Symposium on Circuits and Systems (ISCAS'2013), IEEE International Conference on Computer Design (ICCD'2013),  IEEE International Symposium on Low Power Electronics and Design (ISLPED'2014), IFIP/IEEE VLSI-SoC (2014),  IEEE International System-on-Chip Conference, (SOCC'15), the Asia and South Pacific Design Automation Conference (ASP-DAC' 2016 and 2020), IEEE International Conference on Networking, Architecture, and Storage (NAS 2016),  Conference on Advanced Computer Architecture (ARA’2016),  CNCC'2017,  Asia and South-Pacific Design Automation Conference (ASPDAC'2020), and the International Parallel and Distributed Processing Symposium (IPDPS'2021).

Dr. Cong is a successful serial entrepreneur.  He was the founder and the president of Aplus Design Technologies (1999 – 2003), a UCLA spin-off that developed the first commercially available FPGA architecture evaluation tool and physical synthesis tool, which were licensed by most FPGA companies and OEMed to their customers. Aplus was acquired by the Magma Design Automation in 2003 (now part of Synopsys). Dr. Cong was also a co-founder and the chief technology advisor of AutoESL Design Technologies (2006-2011), another UCLA spin-off that commercialized the research from his lab on high-level synthesis (HLS) for automatic synthesis of behavior-level C/C++ specifications into highly optimized RTL code – an effort that many EDA companies tried but failed for over two decades. The AutoESL tool (renamed to Vivado HLS after Xilinx acquisition in 2011) becomes the most successful and most widely used FPGA HLS tool in the history, with over tens of thousands of users worldwide. He was also a co-founder and the chief scientist of Neptune Design Automation (2011-2013), which produced the fastest and most scalable FPGA physical design tool at its time (acquired by Xilinx in 2013).  He was a co-founder, the chairman and chief scientific advisor of Falcon Computing Solutions,  which provides compilation tool and accelerator IPs to enable FPGA-based acceleration for data centers and edge computing (again acquired by Xilinx in 2020).

Dr. Cong has also served on the Technical Advisory Board of a number of EDA and silicon IP companies, such as Atrenta (acquired by Synopsys in 2015), eASIC (acquired by Intel in 2018), Get2Chip (acquired by Cadence in 2003), Inspirit IoT, Magma Design Automation (acquired by Synopsys in 2012), and Microsoft Research Asia (MSRA)

Dr. Cong has graduated 40 PhD students. Two of them are now IEEE Fellows,  six of them got the highly competitive NSF Career Award, one of them received the ACM SIGDA Outstanding Dissertation Award, and another received the EDAA Outstanding PhD Dissertation Award.   Eleven of his students and postdocs are now faculty members in major research universities worldwide, including Colorado State Univ., Cornell, Fudan Univ, Georgia Tech., Peking Univ, Purdue, Simon Fraser, SUNY Binghamton, UCLA, UIUC, and UT Austin. Many others are in key R&D or management positions in various companies related to the information technologies, such as Amazon,  Arista,  Bloomberg,  Broadcom,  Cadence,  Facebook,  GoogleIBM,  Intel,  Micron,  Synopsys,  and Xilinx.   Also, several of Dr. Cong’s PhD students and postdocs were co-founders, together with Dr. Cong, of tthree startups originated from UCLA – Aplus Design Technologies (acquired by Magma in 2003, now part of Synopsys) AutoESL Design Technologies, and Falcon Computing Solutions (both acquired by Xilinx, in 2011 and 2020, respectively).