Professor Cong's Vita

Jingsheng Jason Cong

University of California, Los Angeles
Computer Science Department
4731J Boelter Hall, Los Angeles, California 90095
Tel: (310) 206-2775

Education

  • Ph.D. in Computer Science:  University of Illinois at Urbana-Champaign, 1990
  • M.S. in Computer Science: University of Illinois at Urbana-Champaign, 1987
  • B.S. in Computer Science: Peking University, 1985

Professional Experience

1990–Present: University of California, Los Angeles,

  • Chancellor’s Professor (2008 – present), Computer Science Department
  • Associate Vice Provost – Internationalization  (2010 – present)
  • Director, Center of Domain-Specific Computing (CDSC) (2009 – present)
  • Co-Director, VLSI CAD Laboratory (1991 – present)
  • Department Chair (2005 – 2008), Computer Science Department
  • Professor  (1998 – present); Associate Professor  (1994 – 1998); Assistant Professor (1990 – 1994)

2014–Present: Co-founder, Chief Scientific Advisor, and Chairman of Board of Directors, Falcon Computing Solutions, Inc.

2011–2013: Co-founder, Chief Technology Advisor, and Chairman of Board of Directors, Neptune Design Automation (acquired by Xilinx in Oct. 2013).

2006–2010: Co-founder, Chief Technology Advisor, and Chairman of Board of Directors, AutoESL Design Technologies (acquired by Xilinx in Jan. 2011).

2003–2008: Chief Technology Advisor, Magma Design Automation

  1998–2003: Founder and CEO/President, Aplus Design Technologies, Inc. (acquired by Magma in 2003)               

  1994 (summer): Visiting Faculty, Intel Corporation

  1986–1990: Research Assistant, Computer Science Dept., University of Illinois at Urbana-Champaign

Honors and Awards

  • PhD advisor of Bingjun Xiao whose dissertation “Communication Optimization for Customizable Domain-Specific Computing” received the 2016 EDAA Outstanding PhD Dissertation Award.
  • FPGA and Reconfigurable Computing Hall of Fame Program inducted the paper "Flow Map: An Optimal Technology Mapping Algorithm for Delay Optimization in Look-Up Table Based FPGA Designs” into the inaugural class of the Hall of Fame, 2017. 
  • Member of the National Academy of Engineering, among the highest honors that can be accorded to an American engineer “for pioneering contributions to application-specific programmable logic via innovations in field programmable gate array (FPGA) synthesis”, 2017.
  • The ASP-DAC’17 10-Year Retrospective Most Influential Paper Award for the paper entitled “Thermal-Aware 3D IC Placement Via Transformation” published in ASP-DAC in 2007. 
  • IEEE Computer Society Technical Achievement Award (2016), “For setting the algorithmic foundations for high-level synthesis of field programmable gate arrays”.
  • The ASPDAC’15 Ten Year Retrospective Most Influential Paper Award for the paper titled “Thermal-Driven Multilevel Routing for 3-D ICs” published in ASPDAC’2005, Asia South-Pacific Design Automation Conference (ASPDAC), Jan. 20, 2015.
  • The ICCAD’14 Ten Year Retrospective Most Influential Paper Award for the paper titled “A Thermal-Driven Floorplanning Algorithm for 3D ICs” published in ICCAD 2004 Conference, International Conference on Computer-Aided Design (ICCAD), November 3, 2014.
  • Distinguished Alumni Achievement Award from the Department of Computer Science at the University of Illinois at Urbana-Champaign, October 24, 2014.
  • Best Paper Award, 2013 International Conference on Hardware/Software Co-design and System Synthesis (CODES+ISSS 2013) for the paper “Improving Polyhedral Code Generation for High-Level Synthesis”.
  • The 50th Design Automation Conference Prolific Author Award -- DAC 40 Club for publishing 40-49 papers in the first 50 years of DAC.
  • PhD advisor of Dr. Guojie Luo whose thesis entitled "Placement and Design Planning for 3D Integrated Circuits" received the 2013 ACM SIGDA Outstanding PhD Dissertation Award in electronic design automation.
  • 2013 ACM Transactions on Design Automation of Electronic Systems (TODAES) Best Paper Award for "“Automatic Memory Partitioning and Scheduling for Throughput and Power Optimization, ” published in March 2011.
  • Best Paper Award, 2013 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (for the paper “Polyhedral-Based Data Reuse Optimization for Configurable Computing”).
  • 2012 ACM Transactions on Design Automation of Electronic Systems (TODAES) Best Paper Award for "Behavior-Level Observability Analysis for Operation Gating in Low-Power Behavioral Synthesis” published in Nov. 2010.
  • IBM Faculty Award (three times), 2002, 2006, and 2012.
  • Two papers of Dr. Cong and his former students (in FPGA’95 and FPGA’99) were selected for FPGA20: the most significant contributions in the FPGA Symposium from 1992 – 2001.
  • ACM/IEEE A. Richard Newton Technical Impact Award in Electric Design Automation (2011), “for pioneering work on technology mapping for FPGA that has made significant impact to the FPGA research community and industry.”
  • Best Paper Award, IEEE Symposium on Field-Programmable Custom Computing Machines (2011)
  • IEEE Circuits and System (CAS) Society Technical Achievement Award (2010), “for seminal contributions to electronic design automation, especially in FPGA synthesis, VLSI interconnect optimization, and physical design automation.”
  • Best Paper Award, 2009 IEEE Symposium on Application Specific Processors (SASP)
  • Semiconductor Research Corporation Inventor Recognition Award (2009)
  • ACM Fellow (2008),“for contributions to electronic design automation”.
  • Best Paper Award, 2008 Int’l Symposium on High Performance Computer Architecture (HPCA)
  • Semiconductor Research Corporation Inventor Recognition Award (2006)
  • Outstanding Alumni Award of Peking University (2005)
  • Best Paper Award, 2005 International Symposium on Physical Design (ISPD) (April 2005)
  • Best Paper Award, ACM Transaction on Design Automation of Electronic Systems (TODAES) (2005)
  • Distinguished Lecturer, IEEE Circuits and Systems Society (2004-2005)
  • Okawa Foundation Research Grant (2004)
  • Semiconductor Research Corporation Technical Excellence Award (2000), for his work in area "Interconnect Estimation Planning and Synthesis for Deep Sub-micron Designs"
  • IEEE Fellow (2000) “for seminal contributions in computer-aided design of integrated circuits, especially in physical design automation, interconnect optimization, and synthesis of field-programmable gate-arrays.”
  • Semiconductor Research Corporation Inventor Recognition Award (2000)
  • Guest Professorship, Peking University (2000)
  • ACM SIGDA Meritorious Service Award (1998)
  • ACM Recognition of Service Award (1997)
  • Best Paper Award of IEEE Transactions on Computer-Aided Design from IEEE Circuits and System Society (1995)
  • National Science Foundation Young Investigator Award (1993)
  • Northrop Corporation Outstanding Junior Faculty Research Award from UCLA (1993)
  • National Science Foundation Engineering Research Initiation Award (1991)
  • Ross J. Martin Award for Excellence in Research from University of Illinois (1989)
  • DEC Fellowship in Computer Science (1988)
  • Best Graduate Award from Peking University (1985)

Editorship

  • Editorial board member, National Science Review, 2012 – present,
  • Editorial board member of SCIENCE CHINA Information Sciences (SCIS), 2012 – present,
  • Senior Editorial Board of the IEEE Journal on Emerging and Selected Topics in Circuits and Systems (2011 – present)
  • Editorial Board Member of Foundations and Trends in Electronic Design Automation (2005 - present)
  • Advisory Board Member, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (2001-present),
  • Associate Editor of ACM Transactions on Design Automation of Electronic Systems (1995 – 2005)
  • Associate Editor of IEEE Transactions on VLSI Systems (1999 – 2002)
  • Guest Editor of IEEE Transactions on VLSI Systems, Special Issues on Field-Programmable Gate Arrays (1997 – 1998)

Services To Professional Conferences and Symposia (selected)

  • Program Committee Member, IEEE/ACM International Symposium on Microarchitecture (MICRO),  2013
  • Program Committee Member, International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2013
  • Program Committee Member (1995 to 2016), General Chair (1998), Program Chair (1997), Publicity Chair (1996), ACM International Symposium on Field-Programmable Gate-Arrays (FPGA)
  • Program Committee Member (2005 – 2015), International Conference on Field-Programmable Logic and Applications.
  • Program Committee Member (1994 – 2010), Executive Committee (1999 – 2015), Program Co-Chair (1999), Publication Chair (1998), Publicity Chair (1996), IEEE International Symposium on Low Power Electronics and Design (ISLPED)
  • Program Committee Member (1998 – 2003), Steering Committee Member (2004-2006, 2012-2014), International Symposium on Physical Design
  • Program Committee Member (2009 - 2011), IEEE Symposium on Application Specific Processors
  • Organizing Committee Member, Workshop on Robust Optimization, sponsored by Institute for Pure and Applied Mathematics, Nov. 16-19, 2010
  • Program Committee Member (2010, 2013), Design, Automation, and Test in Europe (DATE)
  • Member of Panel Committee (2008 - 2009), Strategy Committee (2005-2007), Program Committee Member (1997-2001), Design Automation Conference (DAC)
  • Program Committee Member and EDA Subcommittee Chair (2009), International Symposium on VLSI Design, Automation and Test (VLSI-DAT)
  • General Co-Chair (2005, 2007), ASICON
  • General Co-Chair (2005), Program Co-Chair (2003), Program Committee Member (2006), Asia South Pacific Design Automation Conference (ASP-DAC)
  • Program Committee Area Chair (1996), Program Committee Member & Session Chair (1993-1996, 2002), IEEE International Conference on Computer- Aided Design (ICCAD).
  • Program Co-Chair for Tools and Methodology Track, 2003, International Conference on Computer Design (ICCD)
  • General Chair (1993), Program Committee Member (1993, 1996), ACM/SIGDA Physical Design Workshop  

Services to Professional Societies

  • Founding member of IEEE Spectrum China Editorial Advisory Committee (2012 – present)
  • Member of selection committee of A.R. Newton Technical Impact Award (2012)
  • Member of the IEEE CASS Industrial Pioneer Award selection committee (2012)
  • Board of Governors, IEEE Circuits and Systems Society (2000 – 2004)
  • Member of Advisory Board of ACM SIGDA (1993 – 1999)

Industry Advisory Boards

  • Member of Technical Advisory Board of Lenovo Group, Limited (2016 – Present)
  • Member of Technical Advisory Board of Inspirit, Inc. (2016 – Present)
  • Member of Technical Advisory Board of Microsoft Research Asia (2013 – Present)
  • Member of Technical Advisory Board of Raytheon Corporation for DARPA TRUST Program (2007 – 2008)
  • Member of Technical Advisory Board of Kilopass Technology Inc. (2004 – 2005)
  • Member of Technical Advisory Board of eASIC Corporation (2001 – present)
  • Member of Technical Advisory Board of Get2Chip, Inc. (2000 – 2003) until its acquisition by Cadence Design Systems in 2003.
  • Member of Technical Advisory Board of Atrenta, Inc. (2002 – 2003; 2007- 2015), acquired by Synopsys in 2015.
  • Member of Technical Advisory Board of Ultima Interconnect Technologies, Inc. (1996 – 2000). Ultima merged with BTA and formed Celestry Technologies, which was acquired by Cadence in 2002.
  • Member of Technical Advisory Board of Magma Design Automation (1997 – 2001).  Magma went IPO in 2001 (Nsdq:LAVA)
  • Consultant to Intel Corporation (1994 – 1998)
  • Member of Technical Advisory Board of DARPA MCM project at Mentor Graphics (1994 – 1996)
  • Member of Technical Advisory Board of Silicon Valley Research (1995 – 1996)

Graduated Students

PhD Graduates

  1. Eugene Ding (Ph.D. 1995), MTS, Bell Laboratories
  2. Patrick Madden (Ph.D. 1998), Professor, State Univ. of New York at Binghamton
  3. Cheng-Kok Koh (Ph.D. 1998), Professor, Purdue University
  4. Yeanyow Hwang (Ph.D. 1999), Senior Software Engineer, Synopsys
  5. Chang Wu (Ph.D. 1999), Senior Engineer, Magma Design Automation
  6. Lei He (Ph.D. 1999), Professor, Univ. of California, Los Angeles
  7. Sung-Kyu Lim (Ph.D. 2000), Associate Professor, Georgia Institute of Technology
  8. Sarah Songjie Xu (Ph.D. 2000), Senior Manager, Magma Design Automation
  9. David Zhigang Pan (Ph.D. 2000), Professor, University of Austin, Texas
  10. Jie Fang (Ph.D. 2001), Senior Engineer, Broadcom Corporation
  11. Chin-Chih Chang (Ph.D. 2002), Member of Consulting Staff, Cadence
  12. Tianming (Tim) Kong (Ph.D. 2002), Senior Engineer, Magma Design Automation
  13. Xin Yuan (Ph.D. 2003), EDA Software Developer, IBM Corporation
  14. Michail Romesis (Ph.D. 2005), Member of Technical Staff, Magma Design Automation
  15. Michael Gang Chen (Ph.D. 2005), CEO of Nimbus
  16. Ashok Jagannathan (Ph.D. 2005), Senior Platform Simulation Engineer, Intel Corporation
  17. Deming Chen (Ph. D. 2005), Associate Professor, University of Illinois at Urbana-Champaign
  18. Kenton Sze, (Ph. D. 2006), Sr. Member of Technical Staff, Magma Design Automation
  19. Yan Zhang (Ph.D. 2006), Sr. Member of Technical Staff, Magma Design Automation
  20. Min Xie (Ph.D. 2006),  Sr. Member of Technical Staff, KBC
  21. Joey Yizhou Lin, (Ph.D. 2006), CEO of Arcadia Design Automation
  22. Yiping Fan, (Ph.D. 2006), manager, Xilinx, Co-founder of AutoESL
  23. Zhiru Zhang (Ph.D. 2007), Assistant Professor, Cornell University, Co-founder of AutoESL
  24. Guoling Han (Ph.D. 2007), Sr. Engineer, AutoESL Design Technologies
  25. Wei Jiang (Ph.D. 2009), Google Inc.
  26. Kirill Minkovich (Ph.D. 2010), Postdoc, HRL Laboratories
  27. Guojie Luo (Ph.D. 2011), Assistant Professor, Peking University, Beijing, China
  28. Yi Zou (Ph.D., 2012), Software Engineer, Arsita Networks
  29. Chunyue Liu (PhD, 2012,) SW engineer, Google
  30. Bin Liu (PhD, 2012), Sr. Architect, Micron.
  31. Karthik Gururaj (PhD, 2013), hardware engineer, Intel Corporation.
  32. Hui Huang (PhD, 2014), Google
  33. Bingjun Xiao (PhD, 2015), Google
  34. Yu-Ting Chen (PhD, 2016), Google
  35. Muhuan Huang (PhD, 2016), Google

MS Graduates

  1. M'lissa Smith (MS 1992)
  2. Antonios Papandreous (MS 1992)
  3. Huy Cao (MS 1993)
  4. Ka-Kei Kwok (MS 1994)
  5. Jenny Z. Li (MS 1994)
  6. Jeff Liao (MS 1995)
  7. John Peck (MS 1995)
  8. Sung Lim (MS 1997)
  9. David Zhigang Pan (MS 1998)
  10. Liding Sun (MS 1999)
  11. Michail Romesis (MS 2001)
  12. Michael (Gang) Chen (MS 2001)
  13. Deming Chen (MS 2001)
  14. Yizhou (Joey) Lin (MS 2002)
  15. Yiping Fan (MS 2003)
  16. Min Xie (MS 2003)
  17. Zhiru Zhang (MS 2003)
  18. Jie Wei (MS 2004)
  19. Guoling Han (MS 2004)
  20. Wei Jiang (MS 2006)
  21. Kirill Minkovich (MS 2006)
  22. Amit Agarwal (MS 2008)
  23. Guojie Luo (MS 2008)
  24. Albert Liu (MS 2009)
  25. Yanshu Fan (MS 2009)
  26. Xiangping Qiu (MS 2010)
  27. Yuhui Huang (MS 2010)
  28. Bo Yuan (MS 2014)
  29. Sen Li (MS 2014)
  30. Mo Xu (MS 2014)
  31. Hassan Kianinejad (MS 2015)
  32. Libo Wang (MS 2016)

Research Interests And Publications

Dr. Cong's research interests include synthesis and layout of VLSI circuits, highly scalable VLSI design algorithms and tools, design and synthesis of programmable circuits and systems, computer architectures, and system-on-a-chip designs. Currently, he is leading a research group of 10 to 12 Ph. D. students, several research staff members, and several M.S. students working in these areas. He has published over 300 research papers and led over 40 research projects funded by DARPA, NSF, SRC, UC MICRO and various industrial sponsors. A complete publications list is attached.

Patents

  • Jason Cong and Bingjun Xiao, US Patent 9,461,649, Issued on October 4, 2016, “Programmable Logic Circuit Architecture Using Resistive Memory Elements”.
  • B. Liu, Z. Zhang and J. Cong, US Patent 8,296,710, Issued on Oct 23, ,2012, "Soft Constraints in Scheduling".
  • Mau-Chung F. Chang, Jason Cong, Adam Kaplan, Mishali Naik, Glenn Reinman, Eran Socher, Sai-Wang Tam and Chunyue Liu, U.S. Patent No. 8,270,316, Issued September 18, 2012, “On-Chip Radio Frequency (RF) Interconnects for Network-on-Chip Designs”
  • Jason Cong and David Z. Pan, U.S. Patent No. 6,408,427, Issued June 18, 2002, “Wire Width Planning and Performance Optimization for VLSI Interconnects”
  • Jason Cong and David Z. Pan, U.S. Patent No. 7,013,253, Issued March 14, 2006, “Method and Apparatus for Calculation of Crosstalk Noise in Integrated Circuits”

Publications