Democratizing IC Designs with Deep Learning and High-Level Synthesis, Taiwan Semiconductor Manufacturing Co., Ltd (TSMC). Hsinchu, Taiwan, March 15, 2024 (Invited Talk),
Scheduling and Physical Design, International Symposium on Physical Design, (ISPD) 2024, Taipei, Taiwan, March 12, 2024 (Invited Talk).
Can We Automate Integrated Circuit Design?, Chinese Association for Science and Technology, USA (CAST-USA), Irvine, CA, October 14, 2023 (Keynote Speech).
Democratizing IC Designs -- with Deep Learning and Automated Microarchitecture Optimization, University of Florida, Gainesville, FL, September 14, 2023 (Distinguished Lecture).
Can We Automate Integrated Circuit Design? Samsung Electronics, South Korea, June 27, 2023 (Invited talk).
Democratizing IC Designs and Customized Computing, ETH, Zurich, Switzerland, May 15, 2023 (Distinguished Lecture).
Can We Automate Integrated Circuit Design? Technion University, Haifa, Israel, May 10, 2023 (Invited talk).
Automated Synthesis of Systolic Arrays for Deep Learning and HPC Acceleration, ChipEx’2023, Tel Aviv, Israel, May 9, 2023 (Invited talk).
Layout Synthesis and Architecture Customization for Quantum Computing, Symposium on Emerging Technologies and Applications, Montreux, Switzerland, April 20, 2023 (Keynote Speech).
Democratizing IC Designs and Customized Computing, King Abdullah University of Science and Technology (KAUST), Saudi Arabia, April 4, 2023 (Invited talk).
Can We Automate Integrated Circuit Design? EPFL, Lausanne, Switzerland, March 2023 (Invited talk).
Qubit Mapping for Reconfigurable Atom Arrays, UCLA Center for Quantum Science and Engineering (CQSE), Los Angeles, CA, January 2023 (Invited talk).
Electronic Design Automation: From Integrated Circuits to Quantum Computing, International Conference on New Trends of Computational and Data Sciences, California Institute of Technology (Caltech), Pasadena, CA, December 20, 2022 (Invited talk).
Democratizing IC Designs and Customized Computing, University of Massachusetts, Amherst , November 29, 2022 (Distinguished Lecture).
FPGAs, Real-Time Processing, and Quantum Computing, Harvard Quantum Initiatives (HQI), Harvard University, Cambridge, MA, November 2022 (Invited talk).
Democratizing IC Designs and Customized Computing, Massachusetts Institute of Technology (MIT), Cambridge, MA, November 2022 (Invited talk).
Democratizing IC Designs and Customized Computing, the 2022 International Conference on Computer-Aided Design (ICCAD), Oct. 31, 2022, San Diego, CA. YouTube link for talk. (Keynote Speech)
Democratizing Customized Computing, the 55th IEEE/ACM International Symposium on Microarchitecture® (MICRO), October 4, 2022, Chicago, IL.(Keynote Speech)
“What are the big opportunities in the next renaissance of EDA?”, 2022 Design Automation Conference (DAC), July 12, 2022, San Francisco, CA (moderator for a research panel with guest panelists including Sankar Basu, Timothy Green, Prith Banerjee, Jan Rabaey, Tim Cheng, and Jayanthi Pallinti).
“Improving GNN-Based Accelerator Design Automation with Meta Learning”, presented at the special research session on “New Perspectives in High-Level Synthesis”, 2022 Design Automation Conference (DAC), July 12, 2022, San Francisco, CA.
“Qubit Mapping and Scheduling: Gap Analysis and Optimal Solutions”, presented in a tutorial with Daniel Tan as par to the half-day tutorial on “Scalable Design-Program-Compilation Optimizations for Quantum Algorithms: Using Quantum Neural Network as a Case Study”, 2022 Design Automation Conference (DAC), July 2022, San Francisco, CA.
Democratize IC Designs and Customized Computing, 35th International Conference on VLSI Design, February 28, 2022 (PST). See video for talk. (Vision Talk)
Automated Synthesis and Architecture Optimization for Deep Learning Accelerator Designs, IEEE CASS Rio Grande do Sul Talks 2022, February 18, 2022. See video for talk. (Invited Talk)
Optimal Systolic Array Design for Deep Learning Acceleration, Road4NN, December 5, 2021. See video of talk. (Keynote Speech)
“Layout Synthesis for Quantum Computing: Gap Analysis and Optimal Solution”, the 2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 8, 2021.(Keynote Speech)
“From Parallelization to Customization-Challenges and Opportunities”, the 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS), May 20, 2021. (Keynote Speech)
"AutoSA: A Polyhedral Compiler for High-Performance Systolic Arrays on FPGAs", FCCM Tutorial 2021 - Productive Construction of High-Performance Systolic Arrays on FPGA, May 12, 2021.
"Real-time Machine Learning at the Edge: Digital or Analog Computing?" DAC 2020 Panel, July 23, 2020
“Design Automation for Customizable Computing”, 25th Asia and South Pacific Design Automation Conference (ASP-DAC ‘2020), Beijing, China, January 20, 2020. (Keynote Speech)
"Democratize Customizable Computing", the SIGARCH Visioning Workshop (co-located with ISCA 2019), Phoenix, AZ, June 23, 2019 (Invited Talk)
“Automating Customizable Computing-Democratizing Accelerator Designs at the Edge and in the Cloud”, the Computing in the 21stCentury Conference (21CCC) and Asia Faculty Summit hosted by Microsoft Research Asia (MRSA) in junction with the MRSA 20-year Anniversary Celebration, Beijing, China, November 6, 2018. (Keynote speech)
"Automatic Customizable Computing - From DSLs to FPGAs for Deep Learning and Beyond", The 31st Symposium on Integrated Circuits and System Design (SBCCI 2018), Bento Gonçalves, Rio Grande do Sul, Brazil, August 29, 2018. (Keynote speech)
“Automating Customizable Computing-Democratizing Accelerator Designs at the Edge and in the Cloud”, The Chinese University of Hong Kong (CUHK), June 19, 2018. (Distinguished Lecture)
"Computing Near the End of Moore‘s Law", ECE Department of Northeastern University, Boston, February, 2018 (Distinguished Lecture)
"Computing Near the End of Moore’s Law", CNCC (China National Computer Congress), Fuzhou, China, October, 2017 (Keynote Speech)
"Characterization and Acceleration for Genomic Sequencing and Analysis", IEEE International Symposium on Workload Characterization, Seattle, WA, October 2017 (Keynote Speech)
"Computing at the End of Moore’s Law", Future Forum, Beijing, August 2017
“Customizable Computing: Options and Opportunities”, Symposium on Emerging Trends in Computing, Montreux, Switzerland, Oct. 10, 2016. (Keynote speech)
“Customizable Computing — From Single-chip to Datacenters”, the 11th Conference on Advanced Computer Architecture (ARA’2016), Weihai, China, Aug. 23, 2016. (Keynote speech)
"Customizable Computing at Datacenter Scale”, the 11th IEEE International Conference on Networking, Architecture, and Storage (NAS 2016), Long Beach, California, August 8, 2016. (Keynote speech)
"Heterogeneous Datacenters: Options and Opportunities", 53rd Design Automation Conference, Austin, 5-9 June 2016 (Invited Talk)
"Compilation for Customized Computing -- From Single-Chips to Data Centers” , the 21st Asia and South Pacific Design Automation Conference (ASP-DAC 2016), Macao, China, Jan. 28, 2016. (Keynote speech)
"Datacenter-Scale Customizable Computing", first International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC'15) Held in conjunction with Super Computing 2015, November 22, 2015(Keynote Speech)
"Machine Learning on FPGAs", the First Workshop on Hardware and Algorithms for Learning On-a-Chip (HALO’2015) co-located at the International Conference on Computer-Aided Design (ICCAD’15), November 5, 2015 (Keynote Speech)
"High-Level Synthesis and Beyond -- from Datacenters to IoTs", ACM Symposium on the 28th international IEEE SoC (System-on-Chip) Conference, Beijing, China, Sept, 2015 (Keynote Speech)
"Automating Customized Computing", International Conference on Field Programmable Technology, Shanghai, China, December, 2014 (Keynote Speech)
"Design Automation Beyond High-Level Synthesis", 22nd IPIP/IEEE VLSI-SoC 2014, Playa del Carmen, Mexico, Octorber, 2014 (Keynote Speech)
"Accelerator-Rich Architectures — From Single-chip to Datacenters" 14th IEEE International Symposium on Low Power Electronics and Design (ISLPED), August, 2014, La Jolla, CA, 2014 (Keynote Speech)
"Computing Beyond Processors", 31st IEEE International Conference on Computer Design (ICCD) 2013, AsheVille, NC, October, 2013 (Keynote Speech)
"Computing Beyong Processors", The IEEE International Symposium on Circuits and Systems (ISCAS) 2013, Beijing, China, May, 2013 (Keynote Speech)
"Are FPGAs suffering Innovator's Dilemma" (video), panel on 21st ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA 2013), Monterey, CA, February 2013. (Panel Moderator)
"Era of Customization and Specialization", Intel Design and Test Technology Conference (DTTC), Portland, Oregon, August 2012 (Keynote Speech)
"High-Level Synthesis Revisited: Progress and Applications", INRIA, Paris, France, July 2012 (Invited Talk)
"High-Level Synthesis Revisited: Progress and Applications", Imperial College London, London, United Kingdom, July 2012 (Invited Talk)
"Era of Customization and Specialization", 2nd Workshop on the Intersections of Computer Architecture and Reconfigurable Logic (CARL), Portland, Oregon, June 2012 (Keynote Speech)
"Parallelization, Customization and Automation for Green Computing", 17th Workshop on Synthesis and System Integration of Mixed Information technologies (SASMI), March 2012 (Keynote Speech)
"Dr. C. L. David Liu, Recipient of 2011 Phil Kaufman Award ", 18th annual Phil Kaufman Award ceremony held by the EDA Consortium (EDAC) and the IEEE Council on EDA (CEDA), November 2011 (Award Presenter Speech). Vedio link (starts 18:00) .
"Era of Customization and Specialization for Energy-Efficient Computing", Northwestern University, November 2011 (Distinguished Lecture)
"Energy-Efficient Computing", UCLA Institue of the Environment and Sustainability, Los Angeles, California, November 2011 (Invited Talk)
"Era of Customization and Specialization", 22nd IEEE International Conference on Application-Specific Systems (ASAP), Santa Monica, California, September 2011 (Keynote Speech)
"Era of Customization and Implications to EDA", 48th Annual Design Automation Conference (DAC), San Diego, California, June 2011 ( Keynote Speech at Synopsys University Reception)
"Energy-Efficient Computing Beyond Parallelization", 9th IEEE Symposium on Application Specific Processors (SASP), San Diego, California, June 2011 (Keynote Speech)
"Hardware acceleration for EDA algorithms", Parallel Algorithms, Programming, Architectures Workshop, San Diego, California, June, 2011 (Invited Talk)
"Architecture Support for Customization and Specialization", Giga-Scale Research Center (GSRC) e-seminar, May 10, 2011 (Invited Talk)
"Customizable Domain-Specific Computing", Global Research Collaboration (GRC) Technology Transfer e-Workshop, February 17, 2011 (Invited Talk)
"Customizable Domain-Specific Computing", 3rd US/China Computer Science Leadership Summit, Beijing, China, June 14, 2010 (Invited Talk)
"Customizable Domain-Specific Computing", Distinguished Lecture at Computer Science Department of UC Irvine , April 30, 2010
"Customizable Domain-Specific Computing", Distinguished Lecture at Computer Science Department of UC San Diego , March 1, 2010
"Customizable Domain-Specific Computing", Harvard EE Seminar Series, Dec. 11, 2009 (Invited Talk)
"Customizable Domain-Specific Computing", International Conference on Field Programmable Logic and Applications (FPL), Prague, Czech Republic, Aug. 31- Sept. 2, 2009 (Keynote Speech)
"Multiband RF-Interconnect for Reconfigurable Network-on-Chip Communications", invited panelist in the panel on Impact of Emerging Interconnect Technologies on SLIP Research Directions at the 11th International Workshop on System Level Interconnect Prediction (SLIP), San Francisco, California, July 2009
"From Milliwatts to Megawatts: The System-Level Power Challenge", Panel at Design Automation Conference, San Francisco, California, July 2009
F.Chang, J. Cong, and G. Reinman (UCLA), "RF-Interconnect and its Applications to NOC Design", 3rd ACM/IEEE International Symposium on Network-on-Chip (NOCS), San Diego, CA, May 2009 (NOCS Tutorial Course)
"Is the Second Wave of HLS the One Industry Will Surf on?", Panel at Design, Automation and Test in Europe (DATE 2009), Nice, France, April 2009
"Customized Computing for Power Efficiency", Panel on "FCCM Research: Beyond the Next 5 Years" at IEEE Symposium on Field-Programmable Custom Computing Machines, Napa Valley, CA, April 2009 (Invited Panelist)
"Algorithmic Foundation for ESL 2.0", Workshop on "High-Level Synthesis: Next Step to Efficient ESL Design" at Asia South-Pacific Design Automation Conference, Yokohama, Japan, Jan. 2009 (Invited Talk)
"A New Generation of Behavior Synthesis Tool and Applications to Domain-Specific Computing", ECE Department Colloquium, University of Illinois at Urbana-Champaign, Nov. 20, 2008 (Invited Speaker)
"3D IC Design Tools and Applications to Microarchitecture Exploration", Summer School on Nanoelectronic Circuits and Tools, The Ecole Polytechnique Federale de Lausanne (EPFL) July 2008 (Invited Lecture)
Synthesis and Optimization Foundation for ESL 2.0", Workshop on "High-Level Synthesis: Back to the Future" at Design Automation Conference, Anaheim, California, June 2008 (Invited Talk)
"Thermal-Aware 3D IC Physical Design and Architecture Exploration," International 3D-System Integration Conference 2008 (3D-SIC2008), May 12-13, 2008, Tokyo, Japan (Invited Talk)
"New Opportunities for High-Level Synthesis", Workshop on "The New Wave of the High-Level Synthesis" at Design, Automation and Test in Europe (DATE 2008), Munich, Germany, March 2008 (Invited Talk)
Alberto Sangiovanni Vincentelli (UCB), Douglas Densmore (UCB), Jason Cong (UCLA), Radu Marculescu (CMU), "System-Level Synthesis - Functions, Architectures, and Communications," ASPDAC 2008, January 21-24, 2008, Seoul, Korea (Invited Talk)
"Compilation for Domain-Specific Computing", Department of Electrical and Computer Engineering, University of Texas at Austin, September 11, 2007 (Distinguished Speaker)
"Compilation of Domain-Specific Computing", CANDE 2007 September 6-8, 2007, Long Beach, CA. (Invited Talk)
"Challenges and Opportunities for System/High-Level CAD and Architectures in FPGAs," Workshop on Grand Challenges in FPGA Research (in junction with International Symposium on FPGAs), February 2007. (Invited Talk)
"Advanced Routing Techniques for Nanometer IC Designs," Routing Tutorial with Tong Gao (Synopsys, Inc.) and Rob A. Rutenbar (Carnegie Mellon Univ.) at the 2006 International Conference on Computer-Aided Design, San Jose, California, November 9, 2006.
"3D - IC Keynote Panel Participant," VLSI Multilevel Interconnection Conference, September 2006.
"Platform Based Behavioral and System Synthesis," 2006 IEEE Electronic Design Process Workshop, April 2006. (Invited Talk)
"Platform Based Behavior-Level and System-Level Synthesis," Distinguished Speaker Seminar Series, Electrical and Computer Engineering, Univ. of Arizona (March 2006)
"xPilot: A Platform-Based System-Level Synthesis for Reconfigurable SOCs," International Symposium on Advanced Reconfigurable Systems, Kyoto, Japan, Canada, December 15-16, 2005.
"Platform-Based Synthesis for Field Programmable SOCs," IEEE 2005 Conference on Field Programmable Technology (FPT?5), Singapore, December 11-14, 2005.
"Large Scale Circuit Placement -- Challenges and Progress", Summer Research Institute at the Ecole Polytechnique Federale de Lausanne (EPFL), Switzerland, July 2005.?(Invited Lecture)
Physical Design Automation,?NSF-SIGDA-SRC Summer School of Design Automation, June 2005. (Invited Talk)
"Large-Scale Circuit Placement: Gap and Progress," University of Toronto Distinguished Lecture Series, University of Toronto, Ontario, Canada, March 24, 2005.
"Challenges and Solutions for Nanometer SOC Designs," Invited Talk at the 2004 International SoC Design Conference, Seoul, Korea, October, 2004.
"Architecture and Synthesis for Power-Efficient FPGA's," (Invited Dinner Speech), 2004 IEEE Electronic Design Process Symposium (EDPS), Monterey, California, April, 2004.
"Large-Scale Circuit Placement: Gap and Promise," Embedded Tutorial presented at the 2003 International Conference on Computer-Aided Design, San Jose, California, November 12, 2003.
"Architecture and Synthesis for Multi-Cycle On-Chip Communication,"Invited Talk at the 2003 International Conference on Hardware/Software Codesign and System Synthesis Newport Beach, California October 1, 2003.
"Architecture and Synthesis for Multi-Cycle On-Chip Communication", Intel Physical Design Research Symposium, August 2003. (Invited Talk)
"Architecture and Synthesis for Multi-Cycle On-Chip Communication," Keynote Speaker, International Rapid System Prototyping Workshop, San Diego, California, June 9, 2003.
"Large-Scale Circuit Placement: The Gap and Promise," Guest Lecturer, Georgia Institute of Technology, Atlanta, Georgia, April 17, 2003.
"Architecture and Synthesis for Multi-Cycle Communication,"Invited Talk at the 2003 International Symposium on Physical Design, Monterrey, California, April 9, 2003.
"Retiming/Pipelining Over Global Interconnects," The Design Automation Professional Interest Committee at IBM Research Seminal Series, Yorktown Heights, New York, June 27, 2002.
"System Level Interconnects," FCRP Interconnect Workshop, University of Albany, June 28, 2002.
"Timing closure Based on Physical Hierarchy," Invited talk at International Symposium on Physical Design, San Diego, Californis, April 2002.
"An Interconnect-Centric Design Flow for Nanometer Technologies," Proceedings of the Workshop on Synthesis And Systems Integration of Mixed Technologies, Nara, Japan, October 9, 2001.
"Physical Hierarchy Generation,"; The 3rd Intel Annual Research Symposium on Synthesis, Portland, Oregon, August 15, 2001.
"PLD Synthesis Algorithms," a tutorial presented at the 38th Design Automation Conference, Las Vegas, June, 2001.
"Timing Closure for Ultra Deep Submicron Designs", Asian and South Pacific Design Automation Conference, Jan 30-Feb 2, 2001.
"An Interconnect-Centric Design Flow for Nanometer Technologies", IBM T. J. Watson Research Center, Yorktown Heights, New York, December 2000.?(Invited Talk)
"Incremental CAD", International Conf. on Computer-Aided Design, San Jose,?California, November 2000.?(Embedded Tutorial)
"An Interconnect-Centric Design Flow for Nanometer Technologies", Invited talk at Motorola's Futures Forum on Circuits, Systems, and Architectures, October 16, 2000.
"The Quest for Synthesis and Layout Timing Closure" (full day tutorial, with Olivier Coudert, Anthony Drumm, and Patrick Groeneveld), the 37th Design Automation Conference, Los Angeles, June 9, 2000.
"Incremental Physical Design" (Invited Talk with Majid Sarrafzadeh), Int'l Symposium on Physical Design, San Diego, CA., April 2000.
"Synthesis Challenges for Next-Generation High-Performance and High-Density PLDs" (Invited Talk), Asia and South Pacific Design Automation Conference Yokohama, Japan, Jan. 2000.
"An Interconnect-Centric Design Flow for Nanometer Technologies" (Invited Talk), Int'l Symp. on VLSI Technology, Systems, and Applications, Taipei, Taiwan, June 1999.
"FPGA Synthesis: Past, Present, and Future" (Keynote Speech), The Sixth Japanese FPGA/PLD Design Conference & Exhibit, Pacifico Yokohama, Japan, June 1998.
"Deep Submicron Layout and Coupling to Logic Synthesis" (invited talk), International Workshop on Logic and Architecture Synthesis (IWLAS'97), Grenoble, France, Dec. 16, 1997.
"VLSI Interconnect Layout Optimization In Deep Submicron Designs", UC Berkeley CAD Seminar Series, Nov. 21, 1997.
"Interconnect Design for Deep Submicron ICs", Embedded Tutorial, IEEE Int'l Conf. on Computer-Aided Design, Nov. 1997.
"Interconnect-Driven Performance Optimization for Deep Submicron Layout Systems" (full day tutorial), the 34th Design Automation Conference, June 13, 1997.
"FPGA Mapping, Retiming, and Pipelining for Performance Optimization", UC Berkeley CAD Seminar Series, Mar. 5, 1997.
"Modeling and Layout Optimization of VLSI Devices and Interconnects in Deep Submicron Design" (embedded tutorial), Asia and South Pacific Design Automation Conference (ASP-DAC), Chiba, Japan, Jan. 1997.
"Performance and Power Optimization in Synthesis and Layout of VLSI Circuits and Systems" (tutorial, with Massoud Pedram), EuroDAC'96, Geneva, Switzerland, Sept. 1996.
"Layout Level Optimization for Low Power" (invited lecture), NATO Advanced Study Institute on Low Power Design in Deep Submicron Electronics, Tuscany, Italy, Aug. 1996.
"Interconnect-Driven Layout for High-Performance VLSI Systems" (invited talk), Intel CAD Symposium on Frontiers of CAD, April 12, 1996.
"Interconnect-Driven Layout Synthesis for High-Performance Low-Power VLSI Systems" (short course), Tsinghua University, Taiwan, Aug. 1995.
"Timing-Driven Design of VLSI" (tutorial, with Raul Camposano and Michael Smith), Asia and South Pacific Design Automation Conf., Chiba, Japan, Aug. 1995.
"Dealing with Physical Effects When Designing Deep Submicron Chips" (keynote speech), Silicon Valley Research Continuing Education Series, Austin, Texas, May 4, 1995.
"Interconnect-Driven Layout Synthesis for High-Performance VLSI Systems" (Distinguished Faculty Speaker), Intel Corporation Design Technology Innovations Workshop, Santa Clara, California, March 1994.
"Architecture, CAD Algorithm, and Application of SRAM-Based FPGAs" (tutorial, with Michael Butts and Stephen Trimberger) IEEE Int'l Conf. on Computer-Aided Design, Santa Clara, CA, Nov. 1993.
"Synthesis and Optimization for FPGA Design" (tutorial, with K. C. Chen), Int'l Conf. on Computer-Aided Design and Computer Graphics, Beijing, China, Aug. 1993.
"Performance Evaluation and Optimization in Layout Synthesis of High-Speed VLSI Systems" (tutorial, with Steve Kang and C. L. Liu), 30th ACM/IEEE Design Automation Conference, Dallas, Texas, June 1993.
"On High-Speed VLSI Interconnects: Analysis and Design" (invited talk with Andrew B. Kahng), IEEE Asian-Pacific Conference on Circuits and Systems, Sydney, Australia, Dec. 1992.
"Provably Good Performance-Driven Global Routing" (invited talk), Dagstuhl Seminar On Theory and Practice of VLSI Layout, Dagstuhl, Germany, Sept. 1991.