This project explores methods and tools for AI-driven FPGA and ASIC design optimization. We explore the following topics: (1) Prediction models that estimate design behavior, performance, power, and resource utilization to guide optimization. (2) Datasets that connect hardware designs and implementation choices with feedback from simulation through physical implementation, supporting model training and benchmarking. (3) Customized agents that combine LLM capabilities with hardware knowledge and design tools across high-level synthesis (HLS) and register-transfer level (RTL) workflows. (4) Formal verification to check correctness during design transformations and (5) Open-source electronic design automation (EDA) tools for synthesis, implementation, and evaluation. Together, these efforts explore the frontier of chip design automation by combining machine intelligence with human intelligence embodied in algorithms and tools.
Topic 1: Customized Agent
a. Can Agents Design Better Chips with a Higher Level Abstraction? (ICCAD' 26)
https://arxiv.org/abs/2609.21157
Large Language Model (LLM) agents are increasingly being explored for chip design, but most existing approaches operate directly at RTL. We ask whether agents can design better chips by leveraging higher-level abstractions. We compare Direct RTL Design, Agent-based HLS Design, Post-Compiler HLS Refinement, and Post-HLS RTL Refinement, and combine Agent-based HLS Design with Post-HLS RTL Refinement as Agent-based HLS with RTL Refinement (AHRR). We use FPGAs as a practical, easy-to-deploy platform for end-to-end evaluation, but note that the design-flow tradeoffs we study are largely independent of the target technology. Across a diverse 11-tasks benchmark suite, AHRR achieves a 2.6x geometric-mean speedup over Direct RTL Design across our benchmark suite. Case studies show that HLS distills design knowledge into abstractions that agents can leverage, while RTL refinement recovers lower-level optimization opportunities. Together, these results make AHRR a promising workflow for agentic chip design.
b. High Level Synthesis in the Agentic Era (Integration' 26)
https://www.sciencedirect.com/science/article/pii/S0167926026002336
High-Level Synthesis (HLS) provides a higher-level programming model for chip design, enabling implementations to be derived from algorithmic specifications, simplifying design verification. With recent advances in large language model (LLM)-based agents, there is growing interest in automating chip design directly at the RTL level, raising questions about the role of HLS in agent-driven workflows. In this work, we compare HLS- and RTL-based agentic design flows and find that the HLS flow remains advantageous, especially in terms of delivering better quality of results for algorithm or application-centric tasks. Building on this observation, we present two agent-based frameworks: AgRefactor for robust software-to-HLS refactoring using structured planning, tool integration, and self-improving memory, and ChipComposer for composing and optimizing hardware systems from tool-generated modules. Experimental results across multiple benchmarks show improvements in correctness, design quality, and optimization capability. This study has two implications: (i) LLM-based agents can effectively leverage the HLS abstraction to achieve better and more scalable chip design automation, and (ii) A combination of machine intelligence (via agents) and human intelligence (embodied in custom optimized algorithms and tools) leads to the best chip design automation solutions.
Topic 2: Prediction Model
a. Robust GNN-based Representation Learning for HLS (ICCAD' 23)
https://ieeexplore.ieee.org/document/10323853
In this paper, we present HARP with a novel hierarchical graph representation of the HLS design. Additionally, HARP decouples the representation of the program and its transformations and includes a neural pragma transformer (NPT) approach to facilitate a more systematic treatment of this process. With the proposed model architecture and graph representation, the prediction performance improved by 29% and the DSE performance improved by 1.15X.
b. Cross-Modality Program Representation Learning for Electronic Design Automation with High-Level Synthesis (MLCAD' 24)
https://dl.acm.org/doi/10.1145/3670474.3685952
We propose ProgSG, a model that allows interaction between the source code sequence modality and the graph modality in a deep and fine-grained way. A pre-training method is proposed based on a suite of compiler's data flow analysis tasks. Experimental results show that design performance predictions are improved by up to 22%, and identifies designs with an average of 1.10× and 1.26× performance improvement in design space exploration (DSE) task compared to HARP and AutoDSE, respectively.
c. Hierarchical Mixture of Experts: Generalizable Learning for High-Level Synthesis (AAAI' 25)
https://arxiv.org/abs/2410.19225
We propose a more domain-generalizable model structure: a two-level hierarchical Mixture of Experts (MoE), that can be flexibly adapted to any GNN model. In the low-level MoE, we apply MoE on three natural granularities of a program: node, basic block, and graph. The high-level MoE learns to aggregate the three granularities for the final decision. We further propose a two-stage training method. Extensive experiments verify the effectiveness of the hierarchical MoE.
d. Iceberg: Enhancing HLS Modeling with Synthetic Data (ICLAD' 25)
https://ieeexplore.ieee.org/abstract/document/11106161/
We study the use of synthetic data to improve HLS modeling. Utilizing agent-generated programs, DSE of pragma configuations and weak labels from learned models, we train a Transformer Neural Process that fit both the actual function and synthetic functions. Iceberg improves the geometric mean modeling accuracy by 86.4% when adapt to six real-world applications with few-shot examples and achieves a 2.47× and a 1.12× better offline DSE performance when adapting to two different test datasets.
Topic 3: Datasets
a. Towards a Comprehensive Benchmark for High-Level Synthesis Targeted to FPGAs (NIPS'23 Dataset & Benchmark Track)
https://neurips.cc/virtual/2023/poster/73635
Existing open-source datasets for training HLS models are limited in terms of design complexity and available optimizations. In this paper, we present HLSyn, the first benchmark that addresses these limitations. It contains more complex programs with a wider range of optimization pragmas, making it a comprehensive dataset for training and evaluating design quality prediction models. The HLSyn benchmark consists of 42 unique programs/kernels, resulting in over 42,000 labeled designs. We conduct an extensive comparison of state-of-the-art baselines to assess their effectiveness in predicting design quality.
b. ML Contest for Chip Design with HLS on Kaggle
https://www.kaggle.com/competitions/machine-learning-contest-for-high-le...
We held the first ML contest for chip design on Kaggle using the HLSyn dataset.
Related Events
a. NSF Workshop on Agents for Chip Design Automation (2026)
https://ai4eda-workshop.github.io/2026/
b. NSF Workshop on AI for Electronic Design Automation (2024)