These are the project archives
Projects Archive
| Title | Description |
|---|---|
| Advanced VLSI CAD Algorithms |
Advanced VLSI CAD Algorithms. Sponsored by NSF Young Investigator Award. |
| Clustering and Partitioning for Very Large-Scale Netlists |
Clustering and Partitioning for Very Large-Scale Netlists. Sponsored by Hewlett-Packard under California MICRO Program, Altera and Fujitsu. |
| Computer-Aided Design of High Performance Wireless Networked Systems |
Computer-Aided Design of High Performance Wireless Networked Systems. Sponsored by ARPA/CSTO. |
| The Distributed Supercomputer Supernet -- A Multi-Service Optical Intelligent Network |
The Distributed Supercomputer Supernet -- A Multi-Service Optical Intelligent Network. Sponsored by ARPA/CSTO. |
| Logic Synthesis and Technology Mapping for FPGAs |
Logic Synthesis and Technology Mapping for FPGAs. Sponsored by Xilinx, Altera, AT&T Bell Lab. and California MICRO Program. Sub-projects: |
| Interconnect Design and Optimization for High-Performance Mixed-Signal MCM Layout |
Interconnect Design and Optimization for High-Performance Mixed-Signal MCM Layout. Sponsored by Defense Advanced Research Project Agency (DARPA), Electronic Technology Office (ETO). Sub-project: |
| Synthesis and Optimization under Physical Hierarchy |
This project investigates novel synthesis algorithms under a given physical hierarchy for early interconnect planning in nanometer technologies. Sponsored by SRC. Sub-projects: |
| Microarchitecture Evaluation and Exploration |
Although the emerging three-dimensional integration technology can significantly reduce interconnect delay, chip area, and power dissipation in nanometer technologies, its impact on overall system performance is still poorly understood due to the lack of tools and systematic flows to evaluate 3D microarchitectural designs. Our contribution is the development of MEVA-3D, an automated physical design and architecture performance estimation flow for 3D architectural evaluation which includes 3D floorplanning, routing, interconnect pipelining and automated thermal via insertion, and associated... |
| System Level Design Automation |
With the increasing of the system complexity, the needs of system level design automation becomes more and more urgent. The maturity of high-level synthesis pushes the desgin abstraction from register-transfer level (RTL) to software programming language like C/C++. However, the state-of-art high-level synthesis tools mainly focus on the module-level optimization and implementation such as the scheduling and binding of operators and controls in a certain C/C++ function. System-level optimizations such as module selection and duplication, communication and memory optimization and system... |
| Architecture and Design Automation for Emerging Technologies |
In this paper we introduce a novel FPGA architecture with RRAM-based programmable interconnects (FPGA-RPI). Programmable interconnects are the dominant part of FPGA. We use RRAMs to build programmable interconnects, and we optimize their structures by exploiting opportunities that emerge in RRAM-based circuits. FPGARPI can be fabricated by the existing CMOS-compatible RRAM process. Using an advanced P&R tool named VPR-RPI which was developed to deal with the novel architecture, a customized CAD flow is provided for FPGA-RPI. We apply this flow to the 20 largest MCNC benchmark circuits... |
| Logic and Physical Level Design Automation |
Reconfigurable computing combines the flexibility of software along with the high performance of hardware and exhibits many advantages including flexibility, reduced time-to-market, lower system costs, and capability of adding new features. However, there are a number of drawbacks associated with reconfigurable devices, such as issues related to timing, placement, and routing. Circuits realized on reconfigurable devices typically occupy more area and operate slower than their application-specific integrated circuit counterparts. However, as the complexity of very large scale integration... |
| Analysis and Architecture for Application Level Reliability |
Single event upsets (SEUs) are a source of concern for correct operation of CMOS circuits. The severity of the problem is increased as the transistor size and supply voltage decrease. In the traditional or numerical notion of correctness, every output has to be correct to the last bit. However, there exist many applications which are resilient to a certain degree of error and whose output is of acceptable quality even in the presence of SEUs. We use the concept of application-level correctness to denote acceptable output (rather than numerical correctness) for such applications. Such... |