Efficient Heuristics for the Minimum Shortest Path Steiner Arborescence Problem with Applications to VLSI Physical Design Read more about Efficient Heuristics for the Minimum Shortest Path Steiner Arborescence Problem with Applications to VLSI Physical Design
Partially-Dependent Functional Decomposition with Applications in FPGA Synthesis and Mapping Read more about Partially-Dependent Functional Decomposition with Applications in FPGA Synthesis and Mapping
Modeling and Layout Optimization of VLSI Devices and Interconnects In Deep Submicron Design Read more about Modeling and Layout Optimization of VLSI Devices and Interconnects In Deep Submicron Design
Buffered Steiner Tree Construction with Wire Sizing for Interconnect Layout Optimization Read more about Buffered Steiner Tree Construction with Wire Sizing for Interconnect Layout Optimization
An Efficient Approach to Simultaneous Transistor and Interconnect Sizing Read more about An Efficient Approach to Simultaneous Transistor and Interconnect Sizing
An Improved Algorithm for Performance-Optimal Technology Mapping with Retiming in LUT-Based FPGA Design Read more about An Improved Algorithm for Performance-Optimal Technology Mapping with Retiming in LUT-Based FPGA Design
Simultaneous Buffer and Wire Sizing for Performance and Power Optimization Read more about Simultaneous Buffer and Wire Sizing for Performance and Power Optimization
Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-based FPGA Design Read more about Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-based FPGA Design
Interconnect Layout Optimization by Simultaneous Steiner Tree Construction and Buffer Insertion Read more about Interconnect Layout Optimization by Simultaneous Steiner Tree Construction and Buffer Insertion
Simultaneous Transistor and Interconnect Sizing Using General Dominance Read more about Simultaneous Transistor and Interconnect Sizing Using General Dominance