Interconnect Design for Deep Submicron ICs Read more about Interconnect Design for Deep Submicron ICs
Large Scale Circuit Partitioning with Loose/Stable Net Removal and Signal Flow Based Clustering Read more about Large Scale Circuit Partitioning with Loose/Stable Net Removal and Signal Flow Based Clustering
Global Interconnect Sizing and Spacing with Consideration of Coupling Capacitance Read more about Global Interconnect Sizing and Spacing with Consideration of Coupling Capacitance
Interconnect Layout Optimization Under Higher-Order RLC Model Read more about Interconnect Layout Optimization Under Higher-Order RLC Model
An Efficient Approach to Multi-layer Layer Assignment with Application to Via Minimization Read more about An Efficient Approach to Multi-layer Layer Assignment with Application to Via Minimization
Analysis and Justification of a Simple, Practical 2 1/2-D Capacitance Extraction Methodology Read more about Analysis and Justification of a Simple, Practical 2 1/2-D Capacitance Extraction Methodology
FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential Circuits Read more about FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential Circuits
Fast Optimal Algorithms for the Minimum Rectilinear Steiner Arborescence Problem Read more about Fast Optimal Algorithms for the Minimum Rectilinear Steiner Arborescence Problem
Performance Driven Global Routing for Standard Cell Design Read more about Performance Driven Global Routing for Standard Cell Design
Efficient Heuristics for the Minimum Shortest Path Steiner Arborescence Problem with Applications to VLSI Physical Design Read more about Efficient Heuristics for the Minimum Shortest Path Steiner Arborescence Problem with Applications to VLSI Physical Design