Multi-Way VLSI Circuit Partitioning Based on Dual Net Representations Read more about Multi-Way VLSI Circuit Partitioning Based on Dual Net Representations
Simultaneous Driver and Wire Sizing for Performance and Power Optimization Read more about Simultaneous Driver and Wire Sizing for Performance and Power Optimization
Acyclic Multi-Way Partitioning of Boolean Networks Read more about Acyclic Multi-Way Partitioning of Boolean Networks
Wiresizing with Driver Sizing for Performance and Power Optimization Read more about Wiresizing with Driver Sizing for Performance and Power Optimization
Optimal Wiresizing Under the Distributed Elmore Delay Model Read more about Optimal Wiresizing Under the Distributed Elmore Delay Model
Beyond The Combinatorial Limit in Depth Minimization For LUT-Based FPGA Designs Read more about Beyond The Combinatorial Limit in Depth Minimization For LUT-Based FPGA Designs
Placement and Placement Driven Technology Mapping for FPGA Read more about Placement and Placement Driven Technology Mapping for FPGA
An Optimal Performance-Driven Technology Mapping Algorithm For LUT-Based FPGAs Under Arbitrary Net-Delay Models Read more about An Optimal Performance-Driven Technology Mapping Algorithm For LUT-Based FPGAs Under Arbitrary Net-Delay Models
On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping Read more about On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping
An Efficient Multilayer MCM Router Based on Four-Via Routing Read more about An Efficient Multilayer MCM Router Based on Four-Via Routing