Intellectual Property Protection by Watermarking Combinational Logic Synthesis Solutions Read more about Intellectual Property Protection by Watermarking Combinational Logic Synthesis Solutions
Multiway Partitioning with Pairwise Movement Read more about Multiway Partitioning with Pairwise Movement
Optimal FPGA Mapping and Retiming with Efficient Initial State Computation Read more about Optimal FPGA Mapping and Retiming with Efficient Initial State Computation
Performance Driven Multi-Layer General Area Routing for PCB/MCM Designs Read more about Performance Driven Multi-Layer General Area Routing for PCB/MCM Designs
Interconnect Performance Estimation Models for Synthesis and Design Planning Read more about Interconnect Performance Estimation Models for Synthesis and Design Planning
Delay-Optimal Technology Mapping for FPGAs with Heterogeneous LUTs Read more about Delay-Optimal Technology Mapping for FPGAs with Heterogeneous LUTs
Challenges and Opportunities for Design Innovations in Nanometer Technologies Read more about Challenges and Opportunities for Design Innovations in Nanometer Technologies
An Efficient Technique for Device and Interconnect Optimization in Deep Submicron Designs Read more about An Efficient Technique for Device and Interconnect Optimization in Deep Submicron Designs
Boolean Matching for Complex PLBs in LUT based FPGAs with Application to Architecture Evaluation Read more about Boolean Matching for Complex PLBs in LUT based FPGAs with Application to Architecture Evaluation
Technology Mapping for FPGAs with Embedded Memory Blocks Read more about Technology Mapping for FPGAs with Embedded Memory Blocks