An Interconnect-Centric Design Flow for Nanometer Technologies Read more about An Interconnect-Centric Design Flow for Nanometer Technologies
Technology Mapping for FPGAs with Nonuniform Pin Delays and Fast Interconnections Read more about Technology Mapping for FPGAs with Nonuniform Pin Delays and Fast Interconnections
Simultaneous Circuit Partitioning/Clustering with Retiming for Performance Optimization Read more about Simultaneous Circuit Partitioning/Clustering with Retiming for Performance Optimization
Interconnect Estimation and Planning for Deep Submicron Designs Read more about Interconnect Estimation and Planning for Deep Submicron Designs
Via Design Rule Consideration in Multi-Layer Maze Routing Algorithms Read more about Via Design Rule Consideration in Multi-Layer Maze Routing Algorithms
Crosstalk Noise Control in Gridless General-Area Routing Read more about Crosstalk Noise Control in Gridless General-Area Routing
Interconnect Delay and Area Estimation for Multiple-Pin Nets Read more about Interconnect Delay and Area Estimation for Multiple-Pin Nets
Cut Ranking and Pruning: Enabling A General And Efficient FPGA Mapping Solution Read more about Cut Ranking and Pruning: Enabling A General And Efficient FPGA Mapping Solution
Relaxed Simulated Tempering for VLSI Floorplan Designs Read more about Relaxed Simulated Tempering for VLSI Floorplan Designs
Interconnect Delay Estimation Models for Synthesis and Design Planning Read more about Interconnect Delay Estimation Models for Synthesis and Design Planning