Timing Closure Based on Physical Hierarchy Read more about Timing Closure Based on Physical Hierarchy
Multilevel Approach to Full-Chip Gridless Routing Read more about Multilevel Approach to Full-Chip Gridless Routing
An Interconnect-Centric Design Flow for Nanometer Technologies Read more about An Interconnect-Centric Design Flow for Nanometer Technologies
Performance-Driven Multi-Level Clustering with Application to Hierarchical FPGA Mapping Read more about Performance-Driven Multi-Level Clustering with Application to Hierarchical FPGA Mapping
An Interconnect Energy Model Considering Coupling Effects Read more about An Interconnect Energy Model Considering Coupling Effects
Performance-Driven Mapping for CPLD Architecture Read more about Performance-Driven Mapping for CPLD Architecture
Simultaneous Logic Decomposition with Technology Mapping in FPGA Designs Read more about Simultaneous Logic Decomposition with Technology Mapping in FPGA Designs