Interconnect Synthesis of Heterogeneous Accelerators in a Shared Memory Architecture Read more about Interconnect Synthesis of Heterogeneous Accelerators in a Shared Memory Architecture
CMOST: A System-Level FPGA Compilation Framework Read more about CMOST: A System-Level FPGA Compilation Framework
On-chip Interconnection Network for Accelerator-Rich Architectures Read more about On-chip Interconnection Network for Accelerator-Rich Architectures
Atlas: Baidu’s Key-value Storage System for Cloud Data Read more about Atlas: Baidu’s Key-value Storage System for Cloud Data
A Novel High-Throughput Acceleration Engine for Read Alignment Read more about A Novel High-Throughput Acceleration Engine for Read Alignment
ARACompiler: A Prototyping Flow and Evaluation Framework for Accelerator-Rich Architectures Read more about ARACompiler: A Prototyping Flow and Evaluation Framework for Accelerator-Rich Architectures
Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks Read more about Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks
Resource-Aware Throughput Optimization for High-Level Synthesis Read more about Resource-Aware Throughput Optimization for High-Level Synthesis
High Efficiency VLSI Implementation of an Edge-directed Video Up-scaler Using High Level Synthesis Read more about High Efficiency VLSI Implementation of an Edge-directed Video Up-scaler Using High Level Synthesis
Minimizing Computation in Convolutional Neural Networks Read more about Minimizing Computation in Convolutional Neural Networks