Designing Scratchpad Memory Architecture with Emerging STT-RAM Memory Technologies Read more about Designing Scratchpad Memory Architecture with Emerging STT-RAM Memory Technologies
Polyhedral-Based Data Reuse Optimization for Configurable Computing Read more about Polyhedral-Based Data Reuse Optimization for Configurable Computing
Architecture Support for Custom Instructions with Memory Operations Read more about Architecture Support for Custom Instructions with Memory Operations
Improving High Level Synthesis Optimization Opportunity through Polyhedral Transformations Read more about Improving High Level Synthesis Optimization Opportunity through Polyhedral Transformations
Optimizing Routability in Large-Scale Mixed-Size Placement Read more about Optimizing Routability in Large-Scale Mixed-Size Placement
Stream Arbitration: Towards Efficient Bandwidth Utilization for Emerging On-Chip Interconnects Read more about Stream Arbitration: Towards Efficient Bandwidth Utilization for Emerging On-Chip Interconnects
Memory Partitioning and Scheduling Co-optimization in Behavioral Synthesis Read more about Memory Partitioning and Scheduling Co-optimization in Behavioral Synthesis
A 60GHz On-Chip RF-Interconnect with λ/4 Coupler for 5Gbps Bi-Directional Communication and Multi-Drop Arbitration Read more about A 60GHz On-Chip RF-Interconnect with λ/4 Coupler for 5Gbps Bi-Directional Communication and Multi-Drop Arbitration
BiN: A Buffer-in-NUCA Scheme for Accelerator-Rich CMPs Read more about BiN: A Buffer-in-NUCA Scheme for Accelerator-Rich CMPs
Static and Dynamic Co-Optimizations for Blocks Mapping in Hybrid Caches Read more about Static and Dynamic Co-Optimizations for Blocks Mapping in Hybrid Caches