FPGA-Accelerated 3D Reconstruction using Compressive Sensing Read more about FPGA-Accelerated 3D Reconstruction using Compressive Sensing
An 8Gb/s/pin 4pJ/b/pin Simultaneous Bidirectional Single-T-Line Dual (Base+RF) Band Mobile Memory I/O Interface with Inter-Channel Interference Suppression Read more about An 8Gb/s/pin 4pJ/b/pin Simultaneous Bidirectional Single-T-Line Dual (Base+RF) Band Mobile Memory I/O Interface with Inter-Channel Interference Suppression
Utilizing RF-I and Intelligent Scheduling for Better Throughput/Watt in a Mobile GPU Memory System Read more about Utilizing RF-I and Intelligent Scheduling for Better Throughput/Watt in a Mobile GPU Memory System
Platform Characterization for Domain-Specific Computing Read more about Platform Characterization for Domain-Specific Computing
An Integrated and Automated Memory Optimization Flow for FPGA Behavioral Synthesis Read more about An Integrated and Automated Memory Optimization Flow for FPGA Behavioral Synthesis
Compilation and Architecture Support for Customized Vector Instruction Read more about Compilation and Architecture Support for Customized Vector Instruction
EM+TV Based Reconstruction for Cone-Beam CT with Reduced Radiation Read more about EM+TV Based Reconstruction for Cone-Beam CT with Reduced Radiation
The DIMM Tree Architecture: A High Bandwidth and Scalable Memory System Read more about The DIMM Tree Architecture: A High Bandwidth and Scalable Memory System
Assuring Application-Level Correctness against Soft Errors Read more about Assuring Application-Level Correctness against Soft Errors
Combined Loop Transformation and Hierarchy Allocation for Data Reuse Optimization Read more about Combined Loop Transformation and Hierarchy Allocation for Data Reuse Optimization