A 20Gb/s 79.5mW 127GHz CMOS Transceiver with Digitally Pre-Distorted PAM-4 Modulation for Contactless Communications Read more about A 20Gb/s 79.5mW 127GHz CMOS Transceiver with Digitally Pre-Distorted PAM-4 Modulation for Contactless Communications
HLScope+: Fast and Accurate Performance Estimation for FPGA HLS Read more about HLScope+: Fast and Accurate Performance Estimation for FPGA HLS
AIM: Accelerating Computational Genomics through Scalable and Noninvasive Accelerator-Interposed Memory Read more about AIM: Accelerating Computational Genomics through Scalable and Noninvasive Accelerator-Interposed Memory
Bandwidth Optimization Through On-Chip Buffer Restructuring for HLS Read more about Bandwidth Optimization Through On-Chip Buffer Restructuring for HLS
Automated Systolic Array Architecture Synthesis for High Throughput CNN Inference on FPGAs Read more about Automated Systolic Array Architecture Synthesis for High Throughput CNN Inference on FPGAs
A 125 GHz Transceiver in 65 nm CMOS Assembled With FR4 PCB Antenna for Contactless Wave-Connectors Read more about A 125 GHz Transceiver in 65 nm CMOS Assembled With FR4 PCB Antenna for Contactless Wave-Connectors
Communication Optimization on GPU: A Case Study of Sequence Alignment Algorithms Read more about Communication Optimization on GPU: A Case Study of Sequence Alignment Algorithms
FP-DNN: An Automated Framework for Mapping Deep Neural Networks onto FPGAs with RTL-HLS Hybrid Templates Read more about FP-DNN: An Automated Framework for Mapping Deep Neural Networks onto FPGAs with RTL-HLS Hybrid Templates
HLScope: High-Level Performance Debugging for FPGA Designs Read more about HLScope: High-Level Performance Debugging for FPGA Designs
Supporting Address Translation for Accelerator-Centric Architectures Read more about Supporting Address Translation for Accelerator-Centric Architectures