The Supercomputer Supernet: A Scalable Distributed Terabit Network Read more about The Supercomputer Supernet: A Scalable Distributed Terabit Network
Simultaneous Driver and Wire Sizing for Performance and Power Optimization Read more about Simultaneous Driver and Wire Sizing for Performance and Power Optimization
LUT-Based FPGA Technology Mapping Under Arbitrary Net-Delay Model Read more about LUT-Based FPGA Technology Mapping Under Arbitrary Net-Delay Model
Channel Density Minimization by Pin Permutation Read more about Channel Density Minimization by Pin Permutation
On the Minimum Density Interconnection Tree Problem Read more about On the Minimum Density Interconnection Tree Problem
On Nominal Delay Minimization in LUT-Based FPGA Technology Mapping Read more about On Nominal Delay Minimization in LUT-Based FPGA Technology Mapping
On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping Read more about On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping
A Simplified Synthesis of Transmission Lines with a Tree Structure Read more about A Simplified Synthesis of Transmission Lines with a Tree Structure
FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs Read more about FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs
Matching-Based Methods for High-Performance Clock Routing Read more about Matching-Based Methods for High-Performance Clock Routing