An Efficient Algorithm for Performance Optimal FPGA Technology Mapping with Retiming Read more about An Efficient Algorithm for Performance Optimal FPGA Technology Mapping with Retiming
Performance-Driven Routing with Multiple Sources Read more about Performance-Driven Routing with Multiple Sources
Optimal Wiresizing for Interconnects with Multiple Sources Read more about Optimal Wiresizing for Interconnects with Multiple Sources
Performance Optimization of VLSI Interconnect Layout Read more about Performance Optimization of VLSI Interconnect Layout
The Supercomputer Supernet Testbed: A WDM-Based Supercomputer Interconnect Read more about The Supercomputer Supernet Testbed: A WDM-Based Supercomputer Interconnect
Multiway VLSI Circuit Partitioning Based on Dual net Representation Read more about Multiway VLSI Circuit Partitioning Based on Dual net Representation
Combinational Logic Synthesis for LUT Based Field Programmable Gate Arrays Read more about Combinational Logic Synthesis for LUT Based Field Programmable Gate Arrays
An Efficient Multilayer MCM Router Based on Four-Via Routing Read more about An Efficient Multilayer MCM Router Based on Four-Via Routing
Optimal Wiresizing Under Elmore Delay Model Read more about Optimal Wiresizing Under Elmore Delay Model