MCAS: Multi-Cycle Architectural Synthesis System

The MCAS system accepts behavioral C and VHDL, performs aggressive high-level synthesis and optimization coupled with physical planning to optimize design performance, and generates RTL implementations together with physical constraints and timing constraints (e.g., multi-cycle path constraints) which serve as guidelines for the downstream tools. The underlying theme of this research is to raise the design abstraction from RTL to higher-level description without losing the physical reality.

The Team

• Professor: Jason Cong

• Student: Yiping Fan, Guoling Han, Wei Jiang, Zhiru Zhang

• Former postdoc: Xun Yang

Download MCAS

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Sponsors

• Gigascale Systems Research Center

• Semiconductor Research Corporation

• Altera Corporation

• National Science Foundation