Yu-Ting Chen is a graduate student in computer science at the University of California, Los Angeles, where he is working toward the Ph.D. degree under the guidance of Prof. Jason Cong. He received the B.S. degrees in both computer science and economics and the M.S. degree in computer science from National Tsing Hua University, HsinTsu, Taiwan, R.O.C., in 2005 and 2007 respectively. During his master study, he studied the sleep transistor sizing and the sleep transistor power-on technique to optimize power-gating design for leakage reduction. He also worked at TSMC as a summer intern to develop in-house power estimation tool in 2005.
His current research interests include the energy-efficient memory system, memory architecture using emerging non-volatile memory technologies, and performance modeling for the memory system. In 2013, he is currently working at Intel as a summer intern. He works on efficient I/O buffer system design targeting at the future generation Intel processors.