Logic and Physical Level Design Automation

Project status: 
completed

Reconfigurable computing combines the flexibility of software along with the high performance of hardware and exhibits many advantages including flexibility, reduced time-to-market, lower system costs, and capability of adding new features. However, there are a number of drawbacks associated with reconfigurable devices, such as issues related to timing, placement, and routing. Circuits realized on reconfigurable devices typically occupy more area and operate slower than their application-specific integrated circuit counterparts. However, as the complexity of very large scale integration systems increases, field-programmable gate array (FPGA) computer-aided design tools need to provide high performance, flexibility, and quality of results. Currently, FPGA place and route tools require runtimes in the order of hours compared to minutes of their application-specific integrated circuit counterparts. This detracts from the inherent advantage of FPGA reprogrammability and flexibility.

Our research focuses on the topic of fast compilation for customizable computing on FPGAs and the development of ultra fast placement and routing algorithms for reconfigurable computing. By making use of novel approaches and elaborate optimization techniques, we are developing a high quality placement tool for heterogeneous FPGAs. Our placer is capable of performing routed wirelength estimation, while simultaneously satisfying the extremely demanding timing constraints imposed by reprogrammable computing applications. We focus both on algorithm innovation (for example, exploring fast analytical placement and multilevel placement and routing) and efficient parallel implementation.

We have been able to design and implement a generic FPGA platform consisting of a platform-dependent architecture (computational logic blocks/slices, BRAMs, I/O pads, and legal sites of block types) as well as design-dependent data structures (blocks, nets, sub-blocks, and sub-nets). We developed parsers to interface with the Xilinx, Altera, and VPR platforms, and an accelerated placer that performs estimation (rough legalization) and correction (wirelength minimization). We embedded our placement engine into a complete flow, from synthesis to routing, and performed routing of the designs with commercial routers. To evaluate the quality of our placement tool we generated a large benchmark suite with designs of up to 850,000 LUTs and 650,000 FFs. Our research has brought 200X speed-up over the current FPGA physical design tools.

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